Sony Electronics Inc

S3 Incorporated, Inc.

Sony Corporation

Sony Corporation of America

William S Herz

Michael T MacKay

David L Rossmere

Robert W Duffy

Lee A Cotterill

Joe McArdle

Ignatius B Tjandrasuwita

Jon Earl Graham

Jose R Alvarez

Yichou Lin

Reena Premi

Sunil S Mahajan

Adaptive dynamic aperture correction

A device performs both 2-tap and 3-tap flicker filtering of non-interlaced lines of computer graphics data to form interlaced lines. The device includes a data packer, a data unpacker, and a filter circuit. The filter circuit combines lines that it receives to form filtered lines. The data packer writes the filtered lines to line buffers while the data unpacker reads the lines stored in the line buffers. The read lines are either sent to the filter circuit for further filtering or are outputted to be displayed as interlaced lines. Both 2-tap and 3-tap flicker filtering can be accomplished by varying the order and/or number of read, write, and filter operations.

System and methods for both 2-tap and 3-tap flicker filtering of

An apparatus simultaneously flicker filters and vertically contracts a plurality of original lines to form compensated lines. The device uses a coefficient calculator and a line processor, both controlled by a controller. The coefficient calculator provides compensation coefficients to the line processor. The line processor forms weighted sums of the original lines, with the weightings determined by the compensation coefficients. The compensation coefficients are chosen to simultaneously implement flicker filtering and vertical contraction. Thus, the weighted sums are the compensated lines.

System and method for simultaneous flicker filtering and overscan

A graphics display system processes text data in a video signal, preferably in the vertical blanking interval, and allows a user to selectively display the text data in real time, search the text data, or obtain a transcript of the data. A digitizer and decoder circuit extracts the text data from a video signal and adds an identifier to the text data. A graphics user interface accelerator stores the text data. Concurrent with adding the identifier and the storage of the text data, the digitizer and decoder circuit adds an identifier to the video and audio data, and the graphics user interface accelerator stores the video and audio data. The identifier added to the video and audio data links such data to the associated text data. In response to a user search request, a host processor scans the stored text data for text data that matches a user selected input, and retrieves the text data matching the user selected input. In response to a user command, the host processor retrieves the video and audio data having an identifier matching the identifier of the retrieved text data. The graphics user interface accelerator displays the video data and plays the retrieved audio data. In response to another user command, the host processor provides the retrieved text data to an external device for printing.

Index and storage system for data provided in the vertical blanking

A method and apparatus for correcting the flicker artifact associated with noninterlaced to interlaced video conversion includes a Set-Interpolative-Threshold comparator function whereby weighted line averaging is used only if the difference in luminance, or other color component, of vertically adjacent pixels in the noninterlaced video exceeds a user set threshold value. When the differential value in luminance, or other color component, is greater than the threshold value, and such line averaging is used, the negative effects of the line averaging, such as blurring and darkening of the resulting video frame, are at least partially corrected by aperture/inverse aperture correction.

Correction of flicker associated with noninterlaced-to-interlaced video

A graphics display system processes a video signal that includes closed caption text. A digitizer and decoder circuit retrieves the closed caption data and formats the data to avoid loss by decimation, to be scalable, and to include an indicator of capture or display. The digitizer and decoder circuit includes ping pong buffers for storing the data. During a first odd field, the closed caption data is stored in the ping buffer and the closed caption data from a previous field is read from the pong buffer. During the even field, the closed caption data is again read from the pong buffer. During the next odd field, the operation is repeated with the functions of the ping and pong buffers reversed. Alternatively the even field may contain the closed caption data. The digitizer and decoder circuit includes a capture or display valid bit in the closed caption data to indicate that the caption data is from the current field. The formatted data and a vertical synchronization signal are provided to a graphics user interface (GUI) accelerator which stores the data in a frame buffer or on disk. Response to the vertical synchronization signal, the GUI accelerator generates an interrupt that is serviced by the host processor which controls the reading and display of the caption data.

Closed captioning processing architecture for providing text data during

A method for high speed playback of digital video data (e.g. D1 or D2 data) in which, at lower speeds, the frames of data to be played back are made of a mixture of consecutive frames of data. The frames of data are mixed by averaging the pixel values over consecutive frames to make up the output frames. For high speed shuttle operation, non-consecutive frames are averaged on a pixel by pixel basis to create shuttle frames. In order to improve the appearance of the output, consecutive shuttle frames contain a common original frame so that a component of the original data spans two output frames.

Variable speed playback of digital video stored in a non-tape media

A video and graphics display system compensates for video tearing caused by reading graphics data from a shared buffer faster than video data is stored into the shared buffer. The video data is arranged in video fields comprising scan lines of pixel data. A processor determines the scan line of overtake of reading graphics data from the buffer at a rate faster than storing video data of a current video field into the buffer. A generator provides at least one video scan line as an interpolation of at least one scan line of the current video field stored in the shared buffer and of at least one scan line of a previous video field stored in the shared buffer. A multiplexer receives video scan lines from the shared buffer and from the generator and provides the video scan lines from the shared buffer to a display if there is no scan line of overtake and provides the interpolated video scan lines from the generator to the display if there is a scan line of overtake.

Method and apparatus for correction of video tearing associated with a

A memory module, a partial address generator, and a controllable pseudo-random number generator are provided to a digital video system for generating values used to perform static/dynamic companding for transfer functions shifting/modifying digital video data. The memory module is used for storing an integrated collection of lookup tables comprising lookup tables having values used to perform linear/non-linear static and dynamic companding. The values used to perform static/dynamic companding are retrieved using composite addresses. During each access, the higher order bits are generated by the partial address generator, and the lower order bits are set to equal the current digital video data value being shifted/modified. The partial address generator generates the higher order bits of the composite address based on a number of companding scheme selection control signals and a pseudo-random number received as inputs. The controllable pseudo-random number generator generates the pseudo-random numbers based on the current value of a digital video control counter. Additionally, in the presently preferred embodiment, a quantization error detector is also provided to generate the dynamic companding scheme selection control signals when quantization errors are detected, thereby controlling and causing dynamic companding to be performed only when it is necessary.

Integrated linear/non-linear static and controllable dynamic companding

A switch assembly that can vary at least two controllable parameters and can vary the upper, lower and any intermediary limits of the switch assembly. The switch assembly has a pair of nested coaxial rotary knobs each attached by shafts to sensors that determine the radial position of a reference point on each knob. The knobs rotate with respect to each other and are constructed to allow rotation of the knobs with one hand. The sensors are attached to the controls of the parameters, such that rotation of the knobs varies the output of the parameters. The sensors are coupled to a magnetic clutch that engages and prevents rotation of one of the knobs, when the knob is rotated into a predetermined radial position. A computer can be connected to the magnetic clutch and sensors. The computer receives input signals from the sensors and produces an output signal to the clutch, to engage the clutch and prevent rotation of the knob in accordance with a computer program.

Variable scale rotary switch

Under one embodiment, a first and a second similarly constituted detector, and an OR gate coupled to the two detectors, are provided to a digital video system. The first detector detects quantization errors of numerically adjacent values in vertically adjacent pixels of a current frame. The second detector detects quantization errors of numerically adjacent values in horizontally adjacent pixels in the current frame. The OR gate is used to determine whether quantization errors of numerically adjacent values are detected in at least one of the two spatial dimensions of pixel adjacency in the current frame. In one variation of this embodiment, a potential quantization error lookup table that supports concurrent lookups for vertically and numerically adjacent quantization error detection as well as horizontally and numerically adjacent quantization error detection is used and shared between the two detectors. In an expanded embodiment, a third similarly constituted detector is further provided, and coupled to the OR gate. The third detector detects quantization errors of numerically adjacent values in temporally adjacent pixels of successive frames. The OR gate is used to determine whether quantization errors of numerically adjacent values are detected in at least one of the three dimensions of pixel adjacency. In a further expanded embodiment, a compensation corrector is further provided, and coupled to the OR gate. The compensation corrector prevents successive shifting/modifying of digital video data of horizontally/vertically/temporally adjacent pixels to the same value otherwise resulting from dynamic companding.

Digital video data quantization error detection as applied to

An assembly of serially coupled XOR gates and an assembly of serially coupled shift register-XOR gate pairs are provided to a digital video system. The two assemblies are serially coupled to each other. The assembly of XOR gates generates a shift-in bit for the assembly of shift register-XOR gate pairs based on a cooperatively selected bit of a video control counter and a number of cooperatively selected feedback bits from the XOR gates of the assembly of shift register-XOR gate pairs it received as inputs. The assembly of shift register-XOR gate pairs in turn generates a pseudo-random number based on the shift-in bit and additional cooperatively selected bits of the video control counter. The XOR gate outputs of the assembly of shift register-XOR gate pairs are cooperatively mapped to the various bits of generated pseudo-random number. The pseudo-random number sequence is repeated when the video control counter is reinitialized to a predetermined value and the shift registers are cleared to a predefined state. The sequence length is sufficiently long to outlast a run of the video control counter before it is reinitialized for a new instance of the specified area controlled by the video control counter.

Pseudo-random number generator based on a video control counter

An interface circuit for providing asynchronous interrupt service for multiple peripheral devices in accordance with instructions from a host computer includes two dual universal asynchronous receivers-transmitters ('UARTs'), a dual port random-access memory ('RAM') and a microprocessor ('.mu.P'). The dual UARTs selectively read data separately from selected peripheral devices and selectively write that data to the dual port RAM for access by the host computer, and read data from the dual port RAM as stored therein by the host computer and write that data to a selected peripheral device, in accordance with addresses from the .mu.P. Following initiation of an interrupt sequence, the dual port RAM allows the host computer to selectively and asynchronously read data (e.g. from a peripheral device via a dual UART) therefrom and write necessary data or instructions (e.g. for the .mu.P or a peripheral device via a dual UART) thereto for the .mu.P to asynchronously provide interrupt service to the peripheral devices. This interface circuit configuration minimizes idle time for the host computer during interrupt servicing by the .mu.P.

Growing community of inventors

Newark, CA, United States of America

William S Herz