Arm Limited

Displaylink (UK) Limited

Intel Corporation

Brooktree Broadband Holding, Inc.

Virata Corporation

William Robert Stoye

Sean Tristram LeGuay Ellis

Mathieu Jean Joseph Robart

John David Robson

Wing-Tsi Henry Wong

Richard Bruce

Jorn Nystad

Andreas Due Engh-Halstvedt

Ian Rudolf Bratt

Olof Henrik Uhrenholt

Jørn Nystad

Edvard Fielding

Toni Viki Brkic

Samuel Martin

Isidoros Sideris

Antonio Garcia Guirado

Ole Magnus Ruud

Edward Hardy

David Milway

Stephane Forey

Luka Dejanovic

A method of operating a graphics processor to perform ray tracing. The graphics processor includes a ray tracing circuit that can be messaged by the graphics processor's programmable execution unit during execution of a program to perform a respective traversal of the at least one ray tracing acceleration data structure to be traversed for that ray. The ray tracing circuit may need to stop a ray's traversal to return the ray's processing to the programmable execution unit before the ray's traversal is subsequently restarted. In that case, the ray's traversal is restarted from the beginning.

Graphics processing

When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry representing a group of one or more fragments and including an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents. The coverage information for the list entries is then used to set for entries in the list indicative of fragments to be processed for a sub-region, information indicating whether one or more processing operations are eligible to be performed for fragments that entries in the list represent.

Methods and systems for graphics processing using tile based rendering

An instruction (or set of instructions) that can be included in a program to perform a ray tracing acceleration data structure traversal, with individual execution threads in a group of execution threads executing the program performing a traversal operation for a respective ray in a corresponding group of rays such that the group of rays performing the traversal operation together. The instruction(s), when executed by the execution threads in respect of a node of the ray tracing acceleration data structure, cause one or more rays from the group of plural rays that are performing the traversal operation together to be tested for intersection with the one or more volumes associated with the node being tested. A result of the ray-volume intersection testing can then be returned for the traversal operation.

There is provided an instruction, or instructions, that can be included in a program to perform a ray tracing operation, with individual execution threads in a group of execution threads executing the program performing the ray tracing operation for a respective ray in a corresponding group of rays such that the group of rays performing the ray tracing operation together. The instruction(s), when executed by the execution threads will cause one or more rays from the group of plural rays to be tested for intersection with a set of primitives. A result of the ray-primitive intersection testing can then be returned for the traversal operation.

A data processor includes an execution unit that executes instructions to perform data processing operations, a register file operable to store data values for use by and produced by the execution unit, and a buffer intermediate between the register file for providing data values from the register file to the execution unit for use when executing an instruction, and to receive output data values from the execution unit for writing to the register file. Instructions to be executed by the execution unit of the data processor have associated buffer eviction priority indications representative of a priority for eviction from the buffer of an output data value that will be generated when executing the instruction. The buffer eviction priority indications are then used when selecting data values to evict from the buffer.

Data processing systems including an intermediate buffer with controlled data value eviction

There is provided a graphics processor comprising a programmable execution unit operable to execute programs for respective execution thread groups. An eviction checking circuit is provided that is configured to check instructions as they are being fetched for execution from an instruction cache to determine whether the instruction includes any conditional eviction conditions that if not met indicate that the program to which the instruction relates should not continue to be executed for the group of execution threads. The eviction checking circuit is then configured to check whether any conditional eviction conditions are satisfied at this point and either allow the execution unit to continue program execution or cause the thread group to be evicted.

Graphics processing systems with conditional evictions

A data processor is disclosed in which groups of execution threads can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. Two or more execution threads of a thread group are issued to the same execution lane for execution. The two or more execution threads can then be processed by the execution lane successively, such that the execution lane performs the same processing operation successively. This can have the effect of reducing signal transitions, such that the overall energy consumption of the data processor can be reduced.

Issuing execution threads in a data processor

A shader program to be executed by a graphics processor has associated with it a start instruction indication, indicating the instruction in the sequence of instructions for the program at which execution of the program should be started by an execution thread, and includes a set-entry instruction, which, when executed by a thread, will cause the start instruction indication to be modified to indicate a different instruction in the sequence of instructions for the program at which execution of the program should be started by an execution thread. When executing the program, execution threads determine from the start instruction indication associated with the program, the instruction in the sequence of instructions for the program at which they should start execution of the program.

Shader program execution in graphics processing

A graphics processor performs interleaved graphics processing wherein the interleaved graphics processing comprises performing one or more processing operations to generate one or more sub-regions of a first set of graphics data, and performing one or more further processing operations to generate one or more sub-regions of a second set of graphics data that are dependent on the one or more sub-regions of the first set of graphics data prior to performing one or more processing operations to generate one or more further sub-regions of the first set of graphics data.

A method of operating a data processing system comprises maintaining record of a set of processing passes to be performed by processing pass circuitry of the data processing system. The method comprises performing cycles of operation in which it is considered whether or not the data required for a subset of processing passes is stored in a local cache. The subset of processing passes that is considered in a subsequent scan of the record comprises at least one processing pass that was not considered in the previous scan of the record, regardless of whether or not the data considered in the previous scan is determined as being stored in the cache. The method provides an efficient way to identify processing passes that are ready to be performed.

Data processing systems using both a cache and a buffer for processing data

A display control device is connected to and controls a display device. The display control device comprises a frame buffer store, and a control component. The display control device is arranged to receive (S) compressed display data, store (S) the received compressed display data in the frame buffer store, and for each frame refresh of the display device access (S) stored compressed display data, decompress (S) the accessed display data, and output Sthe decompressed display data.

Decompressing stored display data every frame refresh

A method of generating an image comprises receiving a signal over a USB interface comprising encoded display data for one or more rectangular group of pixel tiles within an image and position data for the or each group of pixel tiles. The coefficients are obtained from the encoded display data, maybe by converting variable bit length fields into AC coefficients and an inverse Haar transform performed on them to generate pixel data for each rectangular group of pixel tiles. A frame buffer, which may be part of the display, is then updated with the generated pixel data ready for output to the display device. Copy protection may also be incorporated using AES negotiated over HDPC.

Image generation

We describe an ultra wideband (UWB) orthogonal frequency division multiplexed (OFDM) modified dual carrier modulation (MDCM) decoder comprising: first and second inputs to input first and second signals for first and second OFDM carriers; third and fourth inputs for respective third and fourth signals comprising channel quality estimates for the OFDM carriers; a set of integer arithmetic units coupled to said first, second, third and fourth inputs to form a set of intermediate terms; a first set of adders to form first and second sets of combinations of said intermediate terms, one for each MDCM coded bit value; a compare-select stage to select a first and second minimum valued said combination of said intermediate terms from said first and second set; and a subtracter to determine a log likelihood ratio (LLR) value for said bit from said first and second minimum valued combinations.

Signal decoding systems

A method and apparatus for scheduling the transmission of cells onto an network, or other packet switching network, is disclosed. The central feature of the scheduling mechanism is a quality of service engine (QoS Engine) which accelerates the processing of packets in a packet switching networks, such as an ATM network, by assisting the accurate pacing of many ATM virtual circuits. The QoS Engine allows the concurrent support of a wide variety of port speeds, traffic classes using different priorities and traffic parameters. quality of service engine (QoS Engine) works in conjunction with a network processor (NP) to allow it to maintain software flexibility, and for it to achieve accurate pacing.

System and method for providing quality of service in asynchronous transfer mode cell transmission

A communication system comprises an input-output processor IOP ( ) coupled to a plurality of network devices ( ) and a protocol processor PP ( ), both processors being coupled to a common memory ( ). Memory access control means ( ) resolves competition between the processors for memory access. Normally, if one of the two processors is accessing the memory, the memory control unit ( ) allows that access to be completed before allowing the other processor to access the memory. But if data loss in a network device is imminent, the IOP, is granted a higher priority memory access, the memory access controller aborts (interrupts) any memory access by the PP, allowing the IOP to access the memory immediately.

Growing community of inventors

Cambridge, United Kingdom

William Robert Stoye