International Business Machines Corporation

Other

Infineon Technologies Ag

Globalfoundries Inc.

William Robert Reohr

Philip George Emma

Phillip John Restle

Jason D Hibbeler

Roy E Scheuerlein

Liang-Teck Pang

Rajiv V Joshi

John Edward Barth, Jr

Li-Kong Wang

Alan J Drake

Thomas J Bucelot

Michael G R Thomson

Joel Abraham Silberman

Yuen H Chan

Birgit Monika Pfitzmann

Robert Allen Groves

Yu Lu

Peter Urbanetz

Yong I Kim

Sang Hoo Dhong

Robert K Montoye

Paul Christian Parries

Matthew R Wordeman

Ferenc Miklos Bozso

Pong-Fei Lu

Alejandro Gabriel Schrott

James Norris Dieffenderfer

John Kenneth DeBrosse

Thomas Philip Speier

Amitkumar Manoharrao Paradkar

Nikolai A Joukov

Dietmar Gogl

Daniel Ray Knebel

Laura A Richardson

Zhigang Hu

Kevin M Kingsbury

William B Yoes

Toshiaki Kirihata

Michael Richard Ouellette

Vijayalakshmi Srinivasan

Hillery C Hunter

Hans Mikael Jacobson

Anthony Correale, Jr

Donald W Plass

Peter Anthony Sandon

Francois Ibrahim Atallah

Gregory Scott Still

Michael Sperling

Allan Mark Hartstein

Wing Kin Luk

Timothy Gerard McNamara

Jeffrey Herbert Fischer

Marc Raymond Faucher

Michael Thomas Fragano

Bryan J Robbins

James Anthony Misewich

Jeffery Howard Oppold

Joshua D Friedrich

Arnold S Tran

Derek H Leu

Robert L Goldiez

Neelesh Govindaraya Pai

Mesut Meterelliyoz

Anthony R Pelella

Daniel Stephen Geise

A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.

Tunable sector buffer for wide bandwidth resonant global clock distribution

A method for controlling the storage of data among multiple regional storage centers coupled through a network in a global storage system is provided. The method includes steps of: defining at least one dataset comprising at least a subset of the data stored in the global storage system; defining at least one ruleset for determining where to store the dataset; obtaining information regarding a demand for the dataset through one or more data requesting entities operating in the global storage system; and determining, as a function of the ruleset, information regarding a location for storing the dataset among regional storage centers having available resources that reduces the total distance traversed by the dataset in serving at least a given one of the data requesting entities and/or reduces the latency of delivery of the dataset to the given one of the data requesting entities.

Method and apparatus for automated migration of data among storage centers

Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.

Setting switch size and transition pattern in a resonant clock distribution system

A classification system executing on one or more computer systems includes a processor and a memory coupled to the processor. The memory includes a discovery engine configured to navigate through non-volatile memory storage to discover an identity and location of one or more files in one or more computer storage systems by tracing the one or more files from file system mount points through file system objects and to disk objects. A classifier is configured to classify the one or more the files into a classification category. The one or more files are associated with the classification category and stored in at least one data structure. The one or more files are classified using an installed storage driver method. Methods are also provided.

System and method for the classification of storage

A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.

Wide bandwidth resonant global clock distribution

A classification system executing on one or more computer systems includes a processor and a memory coupled to the processor. The memory includes a discovery engine configured to navigate through non-volatile memory storage to discover an identity and location of one or more files in one or more computer storage systems by tracing the one or more files from file system mount points through file system objects and to disk objects. A classifier is configured to classify the one or more the files into a classification category. The one or more files are associated with the classification category and stored in at least one data structure. Methods are also provided.

A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.

Defect detection on characteristically capacitive circuit nodes

Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.

Changing resonant clock modes

A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, at least one inductor, at least one tunable resistance switch, and a capacitor network. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.

Variable resistance switch for wide bandwidth resonant global clock distribution

A memory device includes memory cells, each of the memory cells having corresponding bit and word lines connected thereto for accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.

Enhanced data retention mode for dynamic memories

A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.

Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components

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Ridgefield, CT, United States of America

William Robert Reohr