International Business Machines Corporation

Cisco Technology, Inc.

Other

Starlite Electric Inc.

William Robert Lee

Martin Hughes

Trevor Garner

David W Nuechterlein

David Ronny Dwin

Ronald S Svec

John Mitten

Sriram Haridas

Leland D Richardson

Michael L Wright

Kenneth H Potter

Lawrence D Curley

Dennis P Cheney

Darryl Jonathan Rumph

John Kenneth Stacy

Robert Leroy King

David Wallach

Dennis Briddell

Robert Jeter

Paul Stewart Yosim

Trevor Gamer

Joydeep Chowdhury

James Norris Dieffenderfer

Ching-Yun Chao

Richard Gerard Hofmann

Anthony Correale, Jr

Eric M Foster

John William Marshall

Joseph Michael Pennisi

David Carl Frank

Ki Hong Park

Peter Dean LaFauci

Bryan Keith Bullis

Subhrajit Bhattacharya

Michael Patrick Muhlada

Paul S Yosim

Jean-Marc Daveau

Scott Smith

Yan Xiao

Theron Paul Niederer

Paul David Bryan

Rhonda Gurganious Mitchell

Trevor Scott Garner

Reinaldo A Bergamashi/Rab

Neil David Miles

Alan Jay Booker

Hanli Zhang

Ikenna C Osuji

Gegory Goss

Timothy Patrick Oke

Martin W Hughes

A safety garment includes a base layer, and a horizontal, first vertical, and second vertical strip attached to the base layer, and a first and second strip of lighting elements attached to the base layer. The first vertical strip forms at least a first intersection with the horizontal strip. The second vertical strip forms at least a second intersection with the horizontal strip. The first strip of lighting elements is positioned along an outer edge of the first vertical strip. The second strip of lighting elements is positioned along an outer edge of the second vertical strip. A wiring assembly is routed between the base layer and the horizontal strip. An end of the wiring assembly connects to an end of the first vertical strip at the first intersection. Another end of the wiring assembly connects to an end of the second vertical strip at the second intersection.

Safety garment with lights

An approach is provided that authenticates, at an on-line distributor, an end user that has connected to the distributor over a communications network. One or more sets of rules are sent from the distributor to one or more vendor sites. The distributor receives vendor product data pertaining to the vendor sites. The vendor product data received from the vendor sites is based on the sets of rules sent to the respective vendors. A product request is received at the distributor from the authenticated end user. The vendor product data received at the distributor is queried using a query that is based on the product request with the query resulting in a search result that is returned to the end user.

Distributor business policy driven cloud services integration

A fluid shield assembly for preventing fluid from entering a bow of a boat includes a panel that has an outer edge extending between a front side and a back side of the panel. The panel has a pair of slots each extending downwardly from a top side of the outer edge of the panel. The slots are evenly spaced apart from a middle of the top side of the outer edge of the panel to define the door portion of the panel. Each of a plurality of first fasteners engages a boat such that the panel is retained on a bow of the boat. The panel inhibits a fluid from entering the bow of the boat. The door portion of the panel is positioned over a door in the boat to selectively cover and expose the door in the boat.

Fluid shield assembly

Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.

Network protocol header alignment

Techniques for processing requests from a processing thread for a shared resource shared among threads on one or more processors include receiving a bundle of requests from a portion of a thread that is executed during a single wake interval on a particular processor. The bundle includes multiple commands for one or more shared resources. The bundle is processed at the shared resource(s) to produce a bundle result. The bundle result is sent to the particular processor. The thread undergoes no more than one wake interval to sleep interval cycle while the bundle commands are processed at the shared resource(s). These techniques allow a lock for shared resource(s) to be obtained, used and released all while the particular thread is sleeping, so that locks are held for shorter times than in conventional approaches. Using these techniques, line rate packet processing is more readily achieved in routers with multiple multi-threaded processors.

Techniques for reducing thread overhead for systems with multiple multi-threaded processors

An apparatus for routing data packets includes a network interface, a memory, a general purpose processor and a flow classifier. The memory stores a flow structure. Every packet in one flow has identical values for a set of data fields in the packet. The memory stores instruction that cause the processor to receive missing flow data and to add the missing flow to the flow structure. The apparatus forwards a packet based on the flow. The flow classifier determines a particular flow and whether it is already stored in the flow structure. If not, then the classifier determines whether that flow has already been sent to the processor as missing data. If not, then the classifier stores into a different data structure data that indicates the flow has been sent to the processor but is not yet included in the flow data structure, and sends missing data to the processor.

Apparatus for hardware-software classification of data packet flows

Techniques for processing each of multiple threads that share a core processor include receiving an intra-thread register address from the core processor. This address contains C bits for accessing each of 2registers for each thread. A thread ID is received from a thread scheduler external to the core processor. The Thread ID contains T bits for indicating a particular thread for up to 2threads. A particular register is accessed in a register bank that has 2registers using an inter-thread address that includes both the intra-thread register address and the thread ID. The particular register holds contents for the intra-thread register address for a thread having the thread ID. Consequently, register contents of all registers of all threads reside in the register bank. Thread switching is accomplished rapidly by simply accessing different slices in the register bank, without swapping contents between a set of registers and memory.

Techniques for hardware-assisted multi-threaded processing

Method and apparatus for classifying a network protocol and aligning a network protocol header relative to cache line boundary

Techniques for initializing an arbitrary portion of memory with an arbitrary pattern includes using a memory controller for performing sequenced read and write operations. The memory controller receives address data, length data and pattern data on a data bus connected to a processor. The address data indicates a location in memory. The length data indicates an amount of memory to be initialized. The pattern data indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data. The memory controller performs multiple write operations on memory beginning at a first location based on the address data and ending at a second location based on the length data. Each write operation writes the pattern data to a current location in memory, thereby initializing the arbitrary portion of memory with an arbitrary pattern based on the pattern data.

Method and apparatus for arbitrarily initializing a portion of memory

Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned by a DMA controller, for moving data between a data port and a corresponding memory buffer. A write command is placed on a memory exchange queue to change the owner to a different processor and the private index data is incremented. A public index is determined, which indicates a different buffer descriptor in which the owner is most recently changed to the processor and is known to be visible to the processor. In response to receiving a request from the processor for the most recent buffer descriptor changed to processor ownership, the public index data is sent to the processor. Based on the public index data, the processor exchanges data with buffer descriptors guaranteed to be owned by the processor.

Method and apparatus for synchronizing use of buffer descriptor entries for shared data packets in memory

A system and method is provided for automatically identifying and removing malicious data packets, such as denial-of-service (DoS) packets, in an intermediate network node before the packets can be forwarded to a central processing unit (CPU) in the node. The CPU's processing bandwidth is therefore not consumed identifying and removing the malicious packets from the system memory. As such, processing of the malicious packets is essentially 'off-loaded' from the CPU, thereby enabling the CPU to process non-malicious packets in a more efficient manner. Unlike prior implementations, the invention identifies malicious packets having complex encapsulations that can not be identified using traditional techniques, such as ternary content addressable memories (TCAM) or lookup tables.

Hardware filtering support for denial-of-service attacks

A technique efficiently searches a hash table containing a plurality of 'ranges.' In contrast with previous implementations, the technique performs fewer searches to locate one or more ranges stored in the hash table. To that end, the hash table is constructed so each hash-table entry is associated with a different linked list, and each linked-list entry stores, inter alia, 'signature' information and at least one pair of values defining a range associated with the signature. The technique modifies the signature based on the results of one or more preliminary range checks. As a result, the signature's associated ranges are more evenly distributed among the hash table's linked lists. Thus, the linked lists are on average shorter in length, thereby enabling faster and more efficient range searches. According to an illustrative embodiment, the technique is applied to flow-based processing implemented in an intermediate network node, such as a router.

Header range check hash circuit

A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination processor. The bit is positioned in a send register associated with the originating processor and transposed from the send register of the originating processor to a receive register of the destination processor. An interrupt signal is then generated in response to the bit being transposed.

System and method for communicating in a multi-processor environment

The present invention provides a system and method for a plurality of independent processors to simultaneously assemble requests in a context memory coupled to a coprocessor. A write manager coupled to the context memory organizes segments received from multiple processors to form requests for the coprocessor. Each received segment indicates a location in the context memory, such as an indexed memory block, where the segment should be stored. Illustratively, the write manager parses the received segments to their appropriate blocks of the context memory, and detects when the last segment for a request has been received. The last segment may be identified according to a predetermined address bit, e.g. an upper order bit, that is set. When the write manager receives the last segment for a request, the write manager (1) finishes assembling the request in a block of the context memory, (2) enqueues an index associated with the memory block in an index FIFO, and (3) sets a valid bit associated with memory block. By setting the valid bit, the write manager prevents newly received segments from overwriting the assembled request that has not yet been forwarded to the coprocessor. When an index reaches the head of the index FIFO, a request is dequeued from the indexed block of the context memory and forwarded to the coprocessor.

Multi processor enqueue packet circuit

A technique for managing a cache memory coupled to an intermediate node's processor. Packets acquired by the intermediate node that are destined for processing by the processor are tracked, without the processor's intervention, to determine if the processor is lagging in processing the acquired packets. If so, data associated with unprocessed packets are pre-fetched from an external memory and placed in the cache memory without the processor's intervention. Moreover, packets destined for processing by the processor and placed into the cache memory are tracked, without the processor's intervention, to determine if the processor has, in fact, completed the processing of those packets. If so, data contained in the cache memory that is associated with the processed packets are invalidated, again without the processor's intervention.

Pre-fetching and invalidating packet information in a cache memory

Growing community of inventors

Apex, NC, United States of America

William Robert Lee