Micron Technology Incorporated

High Tide Associates, Inc.

Other

William Richard Akin

Shirish Dnyaneshware Bahirat

Joseph Harold Steinmetz

Eric N Lee

Luca Bert

Jeremy Binfet

Robert W Strong

Albert L Hartman

Aditi P Kulkarni

Benjamin Huang

John Masles

Joe Tomasic

Karl David Schuh

Kevin Roy Brandt

Daniel J Hubbard

Jonathan Mark Haswell

Marc S Hamilton

Brooks R Leman

Jui-Yao Yang

Wendy Lorimer

David A Holmstrom

A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

Memory sub-system sanitization

A system includes a memory and at least one processing device, operatively coupled to the memory, to perform operations including causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device. The PMR utilizes a power protection mechanism to prevent data loss in an event of power loss.

Elastic persistent memory regions

Exemplary methods, apparatuses, and systems include detecting a failure of a first memory subsystem of a plurality of memory subsystems. A first recovery instruction is sent to a second memory subsystem of the plurality of memory subsystems. The first recovery instruction directs the second memory subsystem to recover a first subset of data stored by the first memory subsystem. A second recovery instruction is sent to a third memory subsystem of the plurality of memory subsystems. The second recovery instruction directs the third memory subsystem to rebuild a second subset of data stored by the first memory subsystem. The first and second subsets of data differ from one another.

Cooperative memory subsystem data recovery

Exemplary methods, apparatuses, and systems include allotting an initial amount of volatile memory to a write buffer. The write buffer stores batches of data to be written to non-volatile memory. In response to detecting a trigger to update the write buffer configuration, the volatile memory allotted to the write buffer is reduced.

Dynamic buffer limit for at-risk data

Exemplary methods, apparatuses, and systems include determining that a memory component to be subjected to a background data integrity scan does not currently satisfy an activity threshold. The background data integrity scan is delayed in response to determining memory component does not satisfy the activity threshold. In response to detecting a background data integrity scan trigger event, the background data integrity scan is performed.

Opportunistic background data integrity scans

A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Memory plane access management

A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.

A system includes a first memory device including a non-volatile memory device, a second memory device and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including configuring a system in accordance with a configuration designating an interface standard for exposing a storage element implemented on the first memory device to a first protocol of the interface standard and a persistent memory region (PMR) implemented on the second memory device to a second protocol of the interface standard, and performing at least one system operation based on the configuration.

Enabling devices with enhanced persistent memory region access

A request for an estimated temperature of a memory sub-system including multiple components can be received. A set of component temperature values based on temperature measurements at the components can be identified. A subset of the component temperature values can be generated by removing one or more of the component temperature values from the set of component temperature values based on one or more criteria. The estimated temperature value that estimates the temperature of the memory sub-system can be generated using the subset of the component temperature values.

Estimating the temperature of a memory sub-system

A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to perform operations including detecting a failure to completely erase a block of the plurality of blocks in response to an attempted erasure of the block; receiving a blow fuse command in response to the failure to completely erase the block; and blowing a fuse, of the plurality of fuses, coupled with the block, to make the block electrically inaccessible to the control logic in response to receipt of the blow fuse command.

Handling bad blocks generated during a block erase operation

Systems and methods for allocation of overprovisioned blocks for minimizing write amplification in solid state drives are disclosed. An example system comprises: a plurality of memory devices and a processing device operatively coupled to the memory devices, the controller configured to: determine a value of a data stream attribute associated with a data stream; determine, based on the value of the data stream attribute, an overprovisioning factor associated with the data stream, wherein the overprovisioning factor is calculated to provide a uniform distribution of valid translation unit counts (VTCs) across the data stream; and allocate, based on the overprovisioning factor, a plurality of overprovisioned blocks to the data stream.

Allocation of overprovisioned blocks for minimizing write amplification in solid state drives

In an example, an apparatus may include a memory comprising a number of groups of memory cells and a controller coupled to the memory and configured to track respective invalidation velocities of the number of groups of memory cells and to assign categories to the number of groups of memory cells based on the invalidation velocities.

Growing community of inventors

Morgan Hill, CA, United States of America

William Richard Akin