Applied Materials, Inc.

Lam Research Corporation

Applied Komatsu Technology, Inc.

William Reid Harshbarger

Quanyuan Shang

Kam S Law

Takako Takehara

Dan Maydan

Sanjay D Yadav

Tae Kyung Won

Robert M Robertson

Haruhiro Harry Goto

Mark Hsiao

Yvonne LeGrice

Regina Qiu

Soo Young Choi

Woong-Kwon Kim

Dong-Kil Yim

Qunhua Wang

David R Pirkle

Sheng Sun

Robert I Greene

Chuang-Chuang Tsai

Taekyung Won

Duk-Chul Yun

Sakae Tanaka

Youn-Gyung Chang

Ichiro Shimizu

Robert L Greene

John M White

Felix Leib Kozakevich

Beom Soo Park

Carl A Sorensen

Randall S Mundt

Anwar Husain

David Trussell

Dean R Denison

C Robert Koemtzopoulos

Jeff C Olsen

Guofu J Feng

Timothy M Ebel

Gregory A Roche

Larry Williams

A shadow frame and framing system for semiconductor fabrication equipment comprising a rectangular frame having four edges, the edges forming an interior lip with a top surface and an bottom engagement surface; and a cross beam disposed between at least two edges of the frame, the cross beam having a top surface and a bottom engagement surface, the engagement surface of the cross beam configured to be flush with the engagement surface of the lip; wherein one or more of the engagement surfaces are configured to cover metal interconnect bonding areas on a carrier disposed below the frame. The shadow frame is particularly useful in plasma enhanced chemical vapor deposition (PECVD) applications used to make active matrix liquid crystal displays (AMLCDs) and solar cells.

Shadow frame with cross beam for semiconductor equipment

Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an Hplasma. After subjecting the gate metal to an Hplasma, the gate insulating film is deposited onto the gate. In a second method, first and second layers of gate insulating film are respectively deposited on the gate at a first and second deposition rates. One layer is deposited under Hor argon dilution conditions and has improved insulating conditions while the other layer serves to lower the overall compressive stress of the dual layer gate insulator. In a third method, an nsilicon film is formed on a substrate by maintaining a flow of silane, phosphine and hydrogen gas into a processing chamber at substrate temperatures of about 300&#xb0; C. or less.

Low temperature process for TFT fabrication

A method of silicon layer deposition using a cyclical deposition process. The cyclical deposition process comprises alternately adsorbing a silicon-containing precursor and a reducing gas on a substrate structure. Thin film transistors, such as for example a bottom-gate transistor or a top-gate transistor, including one or more silicon layers may, be formed using such cyclical deposition techniques.

Deposition of silicon layers for active matrix liquid crystal display (AMLCD) applications

A substrate support assembly and method for dechucking a substrate is provided. In one embodiment, a support assembly includes a substrate support having a support surface, a first set of lift pins and one or more other lift pins movably disposed through the substrate support. The first set of lift pins and the one or more lift pins project from the support surface when the pins are in an actuated position. When in the actuated position, the first set of lift pins project a longer distance from the support surface than the one or more other lift pins. In another aspect of the invention, a method for dechucking a substrate from a substrate support is provided. In one embodiment, the method includes the steps of projecting a first set of lift pins a first distance above a surface of a substrate support, and projecting a second set of lift pins a second distance above the surface of the substrate support that is less than the first distance.

Method for dechucking a substrate

A plasma display panel including a low k dielectric layer. In one embodiment, the dielectric layer is comprises a fluorine-doped silicon oxide layer such as an SiOF layer. In another embodiment, the dielectric layer comprises a Black Diamond&#x2122; layer. In certain embodiments, a capping layer such as SiN or SiON is deposited over the dielectric layer.

Plasma display panel with a low K dielectric layer

An organic electroluminescent device comprising an anode layer on a substrate, an organic layer on the anode layer, and a cathode layer on the organic layer. In one embodiment, the cathode layer is subjected to Hplasma prior to deposition of a protective layer over the cathode. In another embodiment, the organic electroluminescent device is encapsulated with an inner encapsulation layer on the cathode layer, and an outer encapsulation layer on the inner encapsulation layer. The inner layer is optimized for adhesion to the cathode layer.

Low temperature process for passivation applications

Provided herein is a method for cleaning a process chamber for semiconductor and/or flat panel display manufacturing. This method comprises the steps of converting a non-cleaning feed gas to a cleaning gas in a remote location and then delivering the cleaning gas to the process chamber for cleaning. Such method may further comprise the step of activating the cleaning gas outside the chamber before the delivery of the gas to the chamber. Also provided is a method of eliminating non-cleaning feed gas from the cleaning gas by cryo condensation.

On-site cleaning gas generation for process chamber cleaning

Processes for controlling thickness uniformity of thin organosilicate films as they are deposited on a substrate, and as they finally result. During deposition of the film, which may be accomplished by CVD, PECVD, rapid thermal processing or the like, the substrate temperature is controlled to establish a temperature profile particularly suited to the extreme temperature sensitivities of the deposition rates of organosilicate films such as those deposited from TEOS as a source material.

Process for controlling thin film uniformity and products produced thereby

A process for removing residue from the interior of a semiconductor process chamber using molecular fluorine gas (F) as the principal precursor reagent. In one embodiment a portion of the molecular fluorine is decomposed in a plasma to produce atomic fluorine, and the resulting mixture of atomic fluorine and molecular fluorine is supplied to the chamber whose interior is to be cleaned. In another embodiment the molecular fluorine gas cleans the semiconductor process chamber without any plasma excitation. Molecular fluorine gas has the advantage of not being a global warming gas, unlike fluorine-containing gas compounds conventionally used for chamber cleaning such as NF, CFand SF.

Fluorine process for cleaning semiconductor process chamber

A method of passivation layer deposition using a cyclical deposition process is described. The cyclical deposition process may comprise alternately adsorbing a silicon-containing precursor and a reactant gas on a substrate structure. Thin film transistors, such as a bottom-gate transistor or a top-gate transistor, including a silicon-containing passivation layer, may be formed using such cyclical deposition techniques.

Deposition of passivation layers for active matrix liquid crystal display (AMLCD) applications

A system for processing substrates within a chamber and for cleaning accumulated material from chamber components is provided. The system includes a reactive species generator adapted to generate a reactive gas species for chemically etching accumulated material from chamber components, and a processing chamber having at least one component with a mirror polished surface which is exposed to the reactive species. Preferably to have the greatest impact on chamber cleaning efficiency, the mirror polished surface is a surface of a component such as a gas distribution plate or a backing plate, and/or is a surface of a plurality of smaller components (e.g., chamber wall liners, a gas conductance line, etc.) so as to constitute a large percentage of the surface area exposed to the reactive species. Most preferably all bare aluminum surfaces which the reactive species contacts are mirror polished.

Method and apparatus for enhanced chamber cleaning

A process for depositing a low dielectric constant layer (k&#x3c;3) on a flat panel display and a flat panel display. The process includes reacting one or more organosilicon compounds with an oxygen containing compound at an RF power level from about 0.345 W/cmto about 1.265 W/cm. The flat panel display includes a plasma display panel having a first substrate, a plurality of barriers deposited on the first substrate, a second substrate, a low dielectric constant layer (k&#x3c;3) deposited on the second substrate, and a plurality of ground electrodes formed between the barriers and the dielectric layer.

Application of carbon doped silicon oxide film to flat panel industry

Growing community of inventors

San Jose, CA, United States of America

William Reid Harshbarger