U.S. Philips Corporation

William Redman-White

Mark Bracey

John B Hughes

A class AB amplifier having an output stage comprising complementary common source transistors (T , T ) has means for setting the quiescent current. These comprise a bias resistor (R ) through which a bias current is passed and which is connected between the gates of transistors (T and T ) to set their voltages. The current through the bias resistor (R ) is derived from two reference transistors (T and T ) which each have the desired quiescent current passed through them by current sources ( ). The gate voltages of the reference transistors (T , T ) are applied across a reference resistor (R ) and the current through the reference resistor (R ) is mirrored (T to T ) to the bias resistor (R ).

Amplifier

A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each conversion stage has an input (,) for receiving a sampled and held current which is connected via a switch (S,) to a first current memory (M,) and via a switch (S,) to a second current memory (M,). The output of the second current memory (M,) is fed via a switch (S,) to one input of a summing junction (,). The output of the first current memory (M,) is fed via a switch (S,) to the input of a comparator (L,) whose output is clocked into a latch (L,) whose Q output is connected to an output (,) as the digital result of the conversion. The Q output of the latch (L,) is also connected to a digital to analogue converter (,) whose analogue output is fed to a second input of the summing junction,via a switch (S,) to form the analogue residue signal for application via output (,) to the next conversion stage in the pipeline. The stage has the advantage that the analogue signal is fed from stage to stage using only one current memory (M,) thus reducing transmission loss and that corruption of the analogue signal by comparator &ldquo;kick back&rdquo; is avoided by using a further current memory (M,) in parallel with the signal path current memory (M,).

Analogue to digital converter

A peak detector comprises a device for storing a value representing the currently detected peak amplitude (C,,C,), a circuit for detecting whether the input signal amplitude exceeds the stored value (D1 to D4), an apparatus for updating the stored value at a fast rate if the input signal amplitude exceeds the stored value by more than a given value (D1/V1, D3/V4), and an apparatus for updating the stored value at a slow rate if the input signal amplitude exceeds the stored value by less than the given value (D2/R2, D3/R3). Analogue and digital versions are described together with their application to data slicers in, for example, teletext decoders.

Peak detector

A digital to anologue converter comprises a plurality of current sources (T.sub.o -T.sub.n) and corresponding selection switches (D.sub.o -D.sub.n) which connect the current sources to an output (3). In order to enable a constant capacitance to be presented at the output (3) regardless of the input digital code a plurality of dummy current sources (T.sub.o -T.sub.n) which take the same form as the current sources (To-T.sub.n) are provided. The dummy current sources have associated selection switches ( D.sub.o -D.sub.n) which are operated by the logical inverse of the code applied to the current sources (T.sub.o -T.sub.n).

Digital to analogue and analogue to digital converters

An amplifier, particularly a CMOS amplifier has a differential input which is fed to six differential pairs. The outputs of the first and third differential pair are combined and fed to inputs of a summing network, while the outputs of the fourth and fifth are combined and fed to inputs of the summing network. The second and sixth differential pairs are arranged to cancel the tail currents of the fifth and third pairs, respectively, when all of the devices are in their active state. Thus, regardless of the common mode input level with respect to the supply rails the output current is provided by four devices giving a constant g.sub.m and slew rate.

CMOS differential amplifier having constant transconductance and slew

A current comparator arrangement has first and second inputs (100, 103), an output (105), and cross-coupled transistors (MP1, MP2) which form a latching circuit. The arrangement also includes current stores (MP3, MP4), the input currents to be compared being fed to the current stores in a selected forward differential order for storage therein during a first portion of a clock period in which the cross-coupled latching circuit is reset. During a second portion of the clock period the input current connections are reversed, thereby reversing their differential order, and the reverse order currents are supplied together with the stored forward order currents to the latching circuit. This cancels common mode and offset currents so that they do not affect the comparison of the input currents.

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Romsey, United Kingdom

William Redman-White