Marvell International Limited

Other

William Randolph Schmidt

Douglas G Keithley

John David Marshall

Gordon R Clark

Randall Don Briggs

A system and method for processing digital images that efficiently buffers pixel data relating to digital images is disclosed. Pixel values are read from an image storage memory and temporarily stored in a buffer memory according to a non-raster pattern. The processing of pixels also occurs according to a more efficient non-raster patter.

Non raster row pixel processing

In one example, a direct memory access controller includes a memory interface, a requestor interface, and an address generator. The memory interface is configured to cause a memory to provide at least a subset of data stored in the memory. The requestor interface is configured to receive a request for a consecutively addressed subset of the data stored in the memory to be provided in a non-consecutive order. The address generator is in communication with the requestor interface and the memory interface. The address generator is configured to, based on the request, sequentially generate non-consecutive addresses of the requested subset of the data to cause the memory to provide the requested subset of data in the requested non-consecutive order.

Non-sequential transfer of data from a memory

A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.

Direct memory access controller with multiple transaction functionality

A system and method for processing digital images that efficiently buffers pixel data relating to digital images is disclosed. Pixel values are read from an image storage memory and temporarily stored in a buffer memory according to a non-raster pattern. The processing of pixels also occurs according to a more efficient non-raster pattern.

The disclosed embodiments relate to a memory controller for retrieving a plurality of data stored in a memory in communication with the memory controller, the plurality of data being characterized by a first arrangement of first and second non-parallel arrays, such as one-dimensional arrays. The first array comprises at least first and second data of the plurality of data and the second array comprises at least the first data and third data of the plurality of data. The memory is operative to provide the at least first and second data of the first array before providing at least the third data of the second array when the memory is accessed based on an address of the first data in the memory and an amount of the plurality of data to provide starting from the address of the first data. The memory controller includes an address receiver operative to receive the address of the first data and a request generator in communication with the address receiver and the memory and operative to cause, based on the received address, the memory to provide the at least first data and third data of the second array before providing at least the second data of the first array.

A direct memory access controller comprises a plurality of registers defining parameters for multiple direct memory access transactions and transfer control circuitry responsive to data in the plurality of registers. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the parameters of the plurality of registers. At least two consecutive data transactions are executed with respect to non-contiguous system locations.

DMA controller executing multiple transactions at non-contiguous system locations

An application specific integrated circuit (ASIC) comprises a first bus that communicates with inputs and outputs of N processing modules, where N is an integer greater than 1. A control module communicates with the first bus and a second bus that is different than the first bus, and that generates first control signals. A routing module communicates with the first bus, receives data via the second bus from a first memory, selectively routes the data to a first of the inputs, and selectively routes one of the outputs to a second of the inputs. The routing module selects the first and second of the inputs based on the first control signals.

Pipeline interposer

Reset circuitry for an integrated circuit is presented. An internal oscillator produces an oscillating signal upon power-up of the integrated circuit. The internal oscillator is not dependent on signals generated outside the integrated circuit. An electro-static discharge blocker circuit receives an external reset signal generated outside the integrated circuit. The electrostatic discharge blocker circuit utilizes the oscillating signal to perform electro-static discharge blocking for the external reset signal to produce an internal reset signal.

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Boise, ID, United States of America

William Randolph Schmidt