Intel Corporation

Digital Equipment Corporation

Hewlett-packard Development Company, L.P.

Compaq Computer Corporation, Inc.

William Ralph Wheeler

Matthew James Adiletta

Gilbert M Wolrich

Debra Bernstein

Donald F Hooper

Daniel Cutter

Michael F Fallon

Timothy J Fennell

Myles Wilde

Aaron Gorius

Chengda Yang

Bradley A Burres

Robert C Rose

Samuel William Ho

King-Wai Chow

James Redfield

James D Guilford

Hugh Wilkinson

Amit Kumar

Duane E Galbi

G Michael Uhler

Douglas Carrigan

Samuel Ho

Lidia Warnes

Hamid Partovi

Durgesh Srivastava

Bassam N Coury

Paul H Dormitzer

Subramania Sudharsanan

Johan G Van De Groenendaal

Douglas E Sanders

John F Brown, Iii

George M Uhler

Christopher F Clark

Matthew I Adiletta

Larry L Biro

William C Madden

Steven W Butler

Rajesh Khanna

Serge Kornfeld

Michael A Case

Michael Leary

Matthew Howard Reilly

Timothy J Fennel

Lai-Wah Hui

Mathew J Adiletta

Thomas M Garrison

Thomas Garrison

Examples described herein relate to memory thin provisioning in a memory pool of one or more dual in-line memory modules or memory devices. At any instance, any central processing unit (CPU) can request and receive a full virtual allocation of memory in an amount that exceeds the physical memory attached to the CPU (near memory). A remote pool of additional memory can be dynamically utilized to fill the gap between allocated memory and near memory. This remote pool is shared between multiple CPUs, with dynamic assignment and address re-mapping provided for the remote pool. To improve performance, the near memory can be operated as a cache of the pool memory. Inclusive or exclusive content storage configurations can be applied. An inclusive cache configuration can include an entry in a near memory cache also being stored in a memory pool whereas an exclusive cache configuration can provide an entry in either a near memory cache or in a memory pool but not both. Near memory cache management includes current data location tracking, access counting and other caching heuristics, eviction of data from near memory cache to pool memory and movement of data from pool memory to memory cache.

Memory thin provisioning using memory pools

All in one mobile computing devices and methods performed by the devices. The all in one mobile computing device includes a processor, memory, and software instructions configured to be executed on the processor to enable the mobile computing device to perform various operations. The all in one device may include various wired and wireless interfaces that enable it to communicate with a wide-range of devices, including smartphones, tablets, laptops, personal computers, smart TVs, and others. The all in one device is capable of being remotely accessed when linked in communication with a second device, and is enabled to aggregate data from various user devices and cloud-based services to create unified data resources. Data that is accessed by the device may be synched with a cloud-based storage service to enable a user to access data from across a range of devices via the all in one device. The all in one device has a form factor that is approximately the size of a credit card, yet is capable of running a full-fledged desktop operating system.

All in one mobile computing device

Techniques for implementing assess to Android applications and native Window application on Android devices and systems. A processor board includes a processor that is configured to run a full version of a Windows operating system and Windows applications. The processor board is configured to be communicatively coupled to the processor board in an Android device, such as a Smartphone or tablet. Upon operations and when the processor board is communicatively coupled to the Android device, a user of the Android device is enabled to selectively run Android applications and Windows applications, with the Windows applications being executed natively on the processor board. The processor board may be implemented in a computing card that is approximately the size of a credit card or smaller, which in turn may be coupled to the Android device via a backpack or similar means. The processor board may also be disposed within the same housing as the Android device.

Integrated android and windows device

A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.

Bit check processors, methods, systems, and instructions to check a bit with an indicated check bit value

Mobile computing device technology and systems and methods using the same are described herein. In particular, mobile computing devices that may serve as a processing component of a disaggregated computing system described, non-integral screens that may be paired with the mobile computing devices, and systems and methods using such devices and screens are described. In some embodiments, the mobile computing device technology includes a mobile computing device that lacks an integral screen, but which is capable of throwing at least video information to a non-integral target screen, e.g., via a paired connection established over a wired or wireless communication interface.

Mobile computing device technology and systems and methods utilizing the same

A remotely managed expandable multi-user computer system is provided. The computer system includes a removable compute cartridge and a removable storage cartridge allowing easy upgrade of the computer system. The computer system self-configures when powered on to allow remote management by another system over a network. Automatic failover support is provided without the need for a separate compute element. A self-configurable removable secure-to-wireless converter to couple to a client computer system allows secure communications between the multi-user system and the client computer system via a wireless network.

Method and apparatus for providing a remotely managed expandable computer system

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Memory controllers for processor having multiple programmable units

A parallel hardware-based multithreaded processor. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread.

Register set used in multithreaded parallel processor architecture

A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.

Parallel multi-threaded processing

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.

Processor having a dedicated hash unit integrated within

Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set

A multiprocessor includes a module configured to collect status data, one or more processing engines, and a push engine. Part of the status data is collected from devices connected to a bus and indicates readiness of the devices to participate in data transfers over the bus. The processing engines schedule transfers of data packets between the processor and the devices. The push engine performs unsolicited transfers of a portion of the status data to the processing engines in response to the module collecting new status data.

Providing real-time control data for a network processor

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD. . . THREAD). The processor maintains execution threads (THREAD. . . THREAD) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD. . . THREAD).

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Memory controller for processor having multiple multithreaded programmable units

A processor such as a parallel hardware-based multithreaded processor () is described. The processor () can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register () being set or cleared and which specifies which bit of the specified register to use as a branch control bit.

Branch instruction for processor with branching dependent on a specified bit in a register

Growing community of inventors

Southborough, MA, United States of America

William Ralph Wheeler