Apple Inc.

Motorola Corporation

Vlsi Technology, Inc.

William R Weier

Ray Chang

Steven F Schicht

Richard Y Wong

Stephen T Flannagan

Kenneth W Jones

Glenn E Starnes

Daniel C Chow

In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.

Clock pulse generation circuit

Systems, apparatuses, and methods for efficiently increasing reliability of memory accesses are described. In various embodiments, write data and write mask data are shifted by redundancy logic in a memory. The redundancy logic receives write data bits, which are segmented into one or more write groups in addition to one or more mask bits and one or more shift bits per write group. If the redundancy logic detects a first shift bit assigned to a first write group is asserted, then the redundancy logic selects a second mask bit assigned to a second write group different from the first write group. Otherwise, a first mask bit assigned to the first write group is selected. Following, the redundancy logic combines the selected mask bit with the first data bit of the first write group.

Redundancy implementation using bytewise shifting

Systems, apparatuses, and methods for efficiently driving level shifted write data are described. In various embodiments, a level-shifting write driver combines a write data bit and a write mask bit that each use a first supply voltage to indicate a logic high level. During a write operation, the driver generates complementary values on two output nodes based on the write data bit. The output nodes use a second supply voltage greater than the first supply voltage. Before a write operation, the driver precharges each of the two output nodes to the second supply voltage. When the write clock enables a write operation and the write mask bit disables the write operation, the level-shifting write driver puts the two output nodes in a tri-state.

Level shifting dynamic write driver

A bit line sensing latch circuit is disclosed. In one embodiment, a latch circuit includes a keeper and a precharge circuit. The keeper may be implemented using a single pair of transistors that are cross-coupled between first and second differential signal nodes. A gate terminal of a first one of the pair of transistors is coupled to the first differential signal node, while the drain terminal of the same transistor is coupled to the second differential signal node. The gate terminal of a second one of the pair of transistors is coupled to the second differential signal node, while its drain terminal is coupled to the first differential signal node. The bitline sensing latch also includes a precharge circuit, and may operates in two phases, a precharge phase and an enable phase.

Bitline sensing latch

A clock circuit configured to generate a falling edge independently of an input clock signal is disclosed. In one embodiment, a clock circuit includes an input circuit coupled to receive an input clock signal. A corresponding first clock signal is provided on a first clock node, while a second clock signal that is a delayed version of the first is provided on a second clock signal. The clock circuit may generate an output clock signal based on the first and second clock signals and a feedback signal received from a functional circuit coupled to receive the output clock signal. The rising edge of the output clock signal is generated dependent upon when the rising edge of the input clock signal is received. The falling edge of the output clock signal is generated by the clock circuit independently of when the falling edge of the input clock signal is received.

Self-timed dynamic level shifter with falling edge generator

A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.

Programmable delay control for sense amplifiers in a memory

A memory utilizing programmable delay circuits to control address buffers. A programmable delay device is provided for each block of a plurality of blocks of the memory device. Each block is associated with a corresponding bit array for storing data for the associated block. The delay device is used to delay activation of sense amplifiers from the time the block is selected which, in turn, corresponds to the duration of the addresses that are provided to the bit array within the block. Each of the delays within each block is programmed by a global fuse circuit, so that all of the blocks are programmed with the same delay. After fabrication of the memory device onto an integrated circuit (IC), all of the data paths within each block are measured under various voltage and temperature conditions to identify the slowest data path of all blocks of the memory device. Once a particular delay is identified for the slowest data path within the memory device, all of the programmable delays within each block are programmed with a corresponding delay. In this manner, all of the sense amplifiers within any selected blocks are activated after the programmed delay to ensure valid data. A similar delay device is provided within the clock control circuitry to pulse-width control the clock signal provided to the address buffers. The global fuse circuit used to program the delay device within each of the blocks is also used to program the delay device within the clock control circuit so that the program delay within the clock control circuit and the data blocks are essentially the same.

Memory utilizing a programmable delay to control address buffers

A buffer circuit (60) that includes a current source (74) having an output, the current source to provide a substantially constant current, a first differential amplifier (62), and a second differential amplifier (66). The current from current source 74 is shared by the first (62) and second (64) differential amplifiers.

Buffer circuit, memory device, and integrated circuit for receiving

A memory has a sense amplifier that provides data onto a global data line that is received by a secondary amplifier. The sense amplifier is precharged to a high voltage and responds to data provided by a selected memory cell on a pair of bit lines. The amplifier is a dynamic amplifier that latches the data but also limits the output voltage swing provided to the secondary amplifier. By limiting the voltage swing on the high-capacitance global data lines, there is significant power savings. The voltage swing that is provided is sufficient for reliable detection by the secondary amplifier.

Dynamic sense amplifier in a memory capable of limiting the voltage

A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers that are coupled to the same global data lines are enabled by clocks that are timed by a common clock signal. The memory has subarrays in which each subarray is divided into blocks. When a block is selected, a corresponding block select signal is generated. The sense amplifiers and the secondary amplifiers that are coupled in common with the enabled sense amplifiers in the selected block are enabled in response to this block select signal. The block select signal that enables the sense amplifiers initiates a secondary amp control signal which, after a programmed delay, enables the secondary amplifier.

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Austin, TX, United States of America

William R Weier