International Business Machines Corporation

Other

Siemens Aktiengesellschaft

Semivation, LLC

Infineon Technologies Ag

Globalfoundries Inc.

William R Tonti

Jack Allan Mandelman

Claude Louis Bertin

Toshiharu Furukawa

Wagdi William Abadeer

Robert J Gauthier, Jr

Carl John Radens

John Atkinson Fifield

Jed Hickory Rankin

Russell J Houghton

Louis L Hsu

Kiran V Chatty

Chih-Chao Yang

Louis Lu-Chen Hsu

Kangguo Cheng

Richard Quimby Williams

Jeffrey Scott Brown

David V Horak

Anthony Richard Bonaccio

Charles W Koburger, Iii

Robert Russell Robison

Erik L Hedberg

Jeffrey P Gambino

Wilbur David Pricer

Roger Allen Booth, Jr

Edward J Nowak

Ramachandra Divakaruni

Wayne Frederick Ellis

Mark Charles Hakey

Wayne John Howell

Howard L Kalter

Yun Shi

Sebastian Theodore Ventrone

Veeraraghavan S Basker

Steven H Voldman

Edward William Kiewra

Rama Divakaruni

Christopher P Miller

Marwan H Khater

Karl Robert Erickson

Phil Christopher Paone

Steven J Holmes

Timothy Dooling Sullivan

Chandrasekharan Kothandaraman

Kenneth Joseph Goodnow

Gary Bela Bronner

William Thomas Motsiff

Hiroyuki Akatsu

Max Gerald Levy

Mark Vincent Pierson

Li-Kong Wang

Louis C Hsu

David Michael Fried

Gregory Gower Freeman

James Marc Leas

John Ulrich Knickerbocker

Dureseti Chidambarrao

Terence B Hook

Son Van Nguyen

James William Adkisson

Dominic Joseph Schepis

Souvick Mitra

JunJun Li

Tom C Lee

Mark William Kellogg

Christopher Stephen Putnam

Matthew R Wordeman

Scott Whitney Gould

Minh H Tong

Fariborz Assaderaghi

Peter H Mitchell

Chung H Lam

Rajiv V Joshi

John J Ellis-Monaghan

Keith Kwong Hon Wong

Ping-Chuan Wang

Michael A Gaynes

Hariklia Deligianni

Toshiaki Kirihata

Thomas Vogelsang

Chengwen Pei

Michael Patrick Chudzik

Michael Richard Ouellette

John Michael Cotte

John Edward Barth, Jr

William Paul Hovis

Vamsi Krishna Paruchuri

James Albert Slinkman

Randy William Mann

Jon Alfred Casey

Chandrasekhar Narayan

Johnathan E Faltermeier

William Joseph Murphy

Michel J Abou-Khalil

Darren Lane Anand

Anilkumar Chinuprasad Bhatt

Paul S Chang

Steven Frederick Oakland

Thomas George Ference

David E Lackey

A method of fabricating a single-crystal silicon photovoltaic cell includes providing a single-crystal silicon wafer and a structural support member. The single-crystal silicon wafer has a first major surface and a second major surface. Each major surface extends along a major surface plane. The single-crystal silicon wafer has a thickness greater than 100 micrometers and a dimension greater than 50 mm. The method further includes mounting the structural support member to the first major surface or to the second major surface. The method further includes reducing thickness of the single-crystal silicon wafer to a thickness less than or equal to 100 micrometers while the single-crystal silicon wafer is mounted to the structural support member. The method further includes providing the first major surface with a diffusion and a metalization grid and providing the second major surface with a back surface contact.

Thin single-crystal silicon solar cells mounted to a structural support member and method of fabricating

A method of cleaving off a daughter single crystal substrate from a parent single crystal substrate includes providing a stress-mandrel and the parent a single crystal substrate. The parent single crystal substrate has a major surface and an edge surface that intersects the major surface. The major surface extends along a major surface plane. The stress-mandrel has a stress-mandrel coefficient of thermal expansion that is higher than the parent single crystal coefficient of thermal expansion. The method includes bonding the stress-mandrel to the major surface, and cooling the parent single crystal substrate and the stress-mandrel. The cooling of the parent single crystal substrate bonded to the stress-mandrel provides a thermal stress in the parent single crystal substrate sufficient to cleave the parent single crystal substrate. The cleaving extends substantially along a plane parallel to the plane of the major surface. In one embodiment the cleaved daughter substrate was used to make a photovoltaic cell.

Method of cleaving a single crystal substrate parallel to its active planar surface and method of using the cleaved daughter substrate

Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.

Extremely thin semiconductor-on-insulator (ETSOI) layer

An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.

Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness

A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.

Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness

In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

High-voltage silicon-on-insulator transistors and methods of manufacturing the same

Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.

Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications

A programmable device includes a substrate (); an insulator () on the substrate; an elongated semiconductor material () on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end () is substantially wider than the second end (), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

Programmable semiconductor device

A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Interconnect structure containing various capping materials for programmable electrical fuses

Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

Anti-fuse device structure and electroplating circuit structure and method

A method of forming a semiconductor structure, including forming a gate structure on a substrate; performing a first angled implantation on a first side of the gate structure to form a first doped region in the substrate, the first doped region partially extends within a channel of the gate structure and the gate structure blocks the first angled implantation from affecting the substrate on a second side of the gate structure; forming sidewall spacers on sidewalls of the gate; and forming a second doped region in the substrate on the second side of the gate, spaced apart from the channel.

Self aligned impact-ionization MOS (I-MOS) device and methods of manufacture

A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.

Layered structure with fuse

Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

Method of fabricating field effect transistors with low k sidewall spacers

The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.

Programmable electrical fuse

A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Interconnect structure containing various capping materials for electrical fuse and other related applications

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Essex Junction, VT, United States of America

William R Tonti