Texas Instruments Corporation

Hitachi, Ltd.

Other

William R McKee

Goro Kitsukawa

Takesada Akiba

Jeffrey E Koelling

Hiroshi Otori

Troy H Herndon

Robert Yung-Hsi Tsu

Gishi Chung

Isamu Asano

Dirk N Anderson

Kent R Carson

Chih-Chen Cho

Jules D Levine

Clarence W Teng

Shinpei Iijima

Ming J Hwang

Jeffrey A McKee

Jack S Kilby

Ming-Jang Hwang

Wilbur A Porter

Chi-Chien Ho

Hugh Pryor McAdams

Thomas Dyer Bonifield

Jiong-Ping Lu

Thomas J Aton

Tsuyoshi Tamaru

Qi-Zhong Hong

Lionel S White, Jr

Nagaraj Narasimh Savithri

William F Richardson

Joe W McPherson

Joseph D Luttmer

Duane E Carter

Wei William Lee

Ashesh Parikh

Charles E Williams

Ching-yuh Tsay

Mark E Mason

Eric F Schulte

Elwin L Johnson

Stephen T Tso

Fred D Fishburn

Robert C Baumann

Cishi Chung

' Shiow-Ming Hsieh

Russell H Murdock

Masato Kunitomo

Shimpei Iijima

The present application is directed to a method of selectively positioning sub-resolution assist features (SRAF) in a photomask pattern for an interconnect. The method comprises determining if a first interconnect pattern option will result in improved circuit performance compared with a second interconnect pattern option, where the first option is designed to be formed with SRAF and the second option is designed to be formed without SRAF. If it is determined that the first option will result in improved circuit performance, the first pattern option is selected as a target pattern and one or more SRAF patterns are positioned to facilitate patterning of the first pattern option. If it is not determined that the first option will result in improved performance, the second pattern option is selected as a target pattern.

Method for positioning sub-resolution assist features

Verifying a process margin for a mask pattern includes receiving the mask pattern for patterning features on a semiconductor wafer. The mask pattern is modified according to a wafer pattern model operable to estimate a wafer pattern resulting from the mask pattern. An intermediate stage model is selected to apply to a portion of the mask pattern, where the intermediate stage model is operable to estimate an intermediate stage of the wafer pattern. A process margin of the portion is verified by selecting a test of the intermediate stage model, and performing the test on the portion to verify the process margin of the portion.

Verifying a process margin of a mask pattern using intermediate stage models

An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layerorof FIGS.-), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer, andof FIGS.and) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (materialof FIGS.and) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.

Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer

A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

System with meshed power and signal buses on cell array

The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode adjacent an insulating region . This base electrode can comprise either polysilicon or a metal. A layer of a first material, such as a siliciding metal, is formed over the base electrode as well as the adjacent insulating region. A self-aligned capacitor electrode can then be formed by reacting the first material with the base electrode and removing unreacted portions of the first material from the insulating region . The capacitor is then completed by forming a dielectric layer over the self-aligned capacitor electrode and a second capacitor electrode over the dielectric layer

Integrated circuit capacitor

A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSi N ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i.e., exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via. According to another embodiment, a silicon surface layer is applied to the exposed surface of the dielectric layer and to the exposed surface of the substrate prior to formation of the nitrided surface layer. A layer of tungsten, tungsten/tungsten nitride, or tungsten nitride is formed to fill the via. After annealing, a tungsten conducting plug is formed with a tungsten-silicon-nitride interface region with the substrate.

Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices

An integrated circuit. The circuit includes a memory cell array including wordlines formed on a substrate and bitlines and capacitors formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

Integrated circuit and method

A dual damascene process. After the via etch, a via protect layer ( ) is deposited in the via ( ). The via protect layer ( ) comprises a material that has a dry etch rate at least equal to that of the IMD ( ) and a wet etch rate that is approximately 100 times that of the IMD ( ) or greater. Exemplary materials include PSG, BPSG, and HSQ. The trench pattern ( ) is formed and both the via protect layer ( ) and IMD ( ) are etched. The remaining portions of the via protect layer ( ) are then removed prior to forming the metal layer ( ).

Yield improvement of dual damascene fabrication through oxide filling

The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode,adjacent an insulating region,. This base electrode,can comprise either polysilicon or a metal. A layer,of a first material, such as a siliciding metal, is formed over the base electrode,as well as the adjacent insulating region. A self-aligned capacitor electrode,can then be formed by reacting the first material,with the base electrode,and removing unreacted portions of the first material,from the insulating region,. The capacitor is then completed by forming a dielectric layer,over the self-aligned capacitor electrode,and a second capacitor electrode,over the dielectric layer

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Plano, TX, United States of America

William R McKee