Texas Instruments Corporation

William R Hunter

Clarence W Teng

Christopher Slawinski

Gordon P Pollack

Robert R Doering

Al F Tasch, Jr

Srikanth Krishnan

Thomas C Holloway

Timothy Alan Rost

Ki-Don Lee

Bradley Scott Young

In one embodiment, an integrated circuit includes an electrically active interconnect line within a dielectric layer having a top and bottom surface, the bottom surface of the dielectric layer being coupled to the top surface of a substrate underlying the dielectric layer. The dielectric layer has horizontally arranged heat dissipating layers. An electrically inactive conductor or cooling fin is located within the dielectric layer at a heat dissipating layer below and closer to the substrate than said active interconnect line. The electrically inactive conductor is coupled to said electrically active interconnect line as an extensions of electrically active interconnect line to dissipate heat therefrom.

Mechanical cooling fin for interconnects

In one embodiment, an integrated circuit includes a heat generating structure within a dielectric region and one or more substantially horizontally arranged heat dissipation layers within the dielectric region. Each heat dissipation layer includes electrically inactive thermally conductive structures, at least two such structures in at least one such layer being substantially horizontally connected and thermally coupled to one another within the layer. The electrically inactive thermally conductive structures cooperate to facilitate dissipation of heat from the heat generating structure. In another embodiment, an integrated circuit includes one or more heat generating structures within a dielectric region and electrically inactive thermal posts formed at least partially within the dielectric region. At least one such post is substantially horizontally connected and thermally coupled to another such post. The electrically inactive thermal posts cooperate to facilitate dissipation of heat from the one or more heat generating structures.

INTEGRATED CIRCUIT PROVIDING THERMALLY CONDUCTIVE STRUCTURES SUBSTANTIALLY HORIZONTALLY COUPLED TO ONE ANOTHER WITHIN ONE OR MORE HEAT DISSIPATION LAYERS TO DISSIPATE HEAT FROM A HEAT GENERATING STRUCTURE

The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.

Defect free trench isolation devices and method of fabrication

Method of fabricating defect free trench isolation devices

An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.

Integrated circuit isolation

A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon etch. The first channel stop implant is performed after the first silicon etch, before the sidewall nitride is deposited. A further silicon etch is performed after the sidewall nitride is in place, and a second channel stop implant follows. The first implant can be a light dose, to avoid excess subthreshold leakage in the active devices due to field-assisted turn on at the corners of the moat regions, and the second implant can be a very heavy dose to provide complete isolation without any danger of the channel stop species encroaching on the active device regions.

Channel stop isolation technology utilizing two-step etching and

A method for fabricating a semiconductor device of relatively small scale. A conductivity layer is deposited on a substrate of a polarity. Regions of opposite polarity are partially formed on either side of the conductor layer. Vertical layers are formed to partially cover the regions of opposite polarity and are located adjacent to the conductor layer. Extensions of the regions of opposite polarity are formed such that a portion of the extension is defined by the location of the vertical layers.

Fabrication of submicron semiconductor devices

A method for patterning a submicrometer substrate element which is smaller than the reproducible resolution accuracy of optical lithography. A series of layers is deposited upon a top layer pattern using standard methods. An edge of the top layer is positioned at or near where the required submicrometer element is to be patterned. A cavity is formed in one of the intermediate layers by removing that intermediate layer in such a fashion that the layer underneath the edge of the top layer is removed. Next, a conformal layer is deposited upon the structure so that the conformal layer fills the cavity. Then the conformal layer is removed and each of the other layers is sequentially removed in such a fashion that only that portion of the conformal layer that occupied the cavity remains, together with any layers that occupy the space underneath the cavity. The remaining layers are the mask for further patterning.

Formation of submicron substrate element

A method of fabricating deep grooves having submicron widths in a semiconductor substrate. A pattern of submicron oxidation masking elements formed on the substrate surface serves as an oxidation mask for a thick oxide layer. After forming the oxide layer, the insulating elements are removed to form a pattern of submicron width openings in the oxide extending to the substrate. A selective anisotropic dry etch is then used to form deep, narrow grooves in the substrate conforming to the pattern of openings which are filled with an insulating material formed by thermal oxidation, chemical vapor deposition, or a combination thereof. This process is used to provide deep dielectric isolation between active areas in high density integrated circuits.

Growing community of inventors

Garland, TX, United States of America

William R Hunter