Lucent Technologies Inc.

Agere Systems Inc.

William R Griesbach

Ravi Kumar Kolagotla

Che Choi C Leung

An ESD power clamp utilizes both a transient triggering method integrated together with a voltage level detection circuit to disable a MOSFET transistor forming the ESD power clamp unless the voltage level on a relevant power supply rail is higher than a predetermined level above the normal power supply voltage. When the voltage level of the power supply rail is higher than the predetermined level (e.g., 10% higher, 25% higher, etc.), then the power surge is presumed to be an ESD pulse, and thus the ESD power clamp is enabled to turn ON and discharge the ESD power surge.

Electro-static discharge (ESD) power clamp with power up detection

A squarer generates an array of partial products. A method of squaring a representation of a number includes generating an array of partial products, combining the partial product on one side of a diagonal of the array with partial products on the other side of the diagonal to form a folded array of partial products, and combining each of at least one more than half of the partial products in the diagonal of the array with a corresponding one of the partial products in the folded array to produce a new folded array of partial products. In an alternative embodiment, the present invention is a circuit for squaring an n-bit representation of a number.

Squarer with diagonal row merged into folded partial product array

There is disclosed an integrated circuit including a programmable driver circuit having first and second transistors. Each of the first and second transistors has first, second and third terminals. The first terminal of each of the first and second transistors are coupled together to form an input node. The second terminal of the first transistor is coupled to a power node. A third terminal of the first transistor is coupled to a first intermediate node. The second terminal of the second transistor is coupled to a second intermediate node. The third terminal of the second transistor is coupled to a reference potential. A first switch having at least one input is coupled between the first and second intermediate nodes. Third and fourth transistors each having first, second and third terminals. The first terminal of the third transistor is coupled to a third intermediate node. The first terminal of the fourth transistor is coupled to the second intermediate node. The second terminal of the third transistor is coupled to the power node. The third terminal of the third transistor is coupled to the second terminal of the fourth transistor to define an output node. The third terminal of the fourth transistor is coupled to the reference potential. A second switch having at least one control input is coupled between the third intermediate node and the first intermediate node.

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Pocono Pines, PA, United States of America

William R Griesbach