International Business Machines Corporation

William R Greer

Christopher M Herring

Ralph M Begun

John Edward Derrick

Richard P Abato

Buffers are provided in a computer system to allow posting data to the buffers, followed by concurrent operation by different portions of the computer system. A CPU buffer is provided to buffer CPU accesses, a CPU-to-PCI buffer is provided to buffer CPU accesses to the PCI local bus, and a memory buffer is provided to buffer CPU accesses to main memory. This configuration allows the CPU-to-PCI buffer to write data concurrently with the memory buffer accessing data from main memory.

Computer system buffers for providing concurrency and avoid deadlock

Computer system buffers for providing concurrency between CPU accesses,

A personal computer system is provided which includes a CPU, with the CPU being operable by a BIOS including initialization or booting instructions. The system includes a local bus and a peripheral bus. A bus interface chip, including a memory controller/peripheral bus host bridge (MC/PBHB) interconnects the local bus and the peripheral bus, and includes a latch which includes as its input clock cycles generated by the CPU. The initialization instructions of the BIOS are contained in a non-volatile ROM module located to write onto either the local bus or the peripheral bus. The MC/PBHB unit is able to decode and handle ROM cycles and is configured to either pass or not pass ROM read cycles depending upon certain control states that identify whether the ROM is located on the local bus or the peripheral bus. Logic is provided to detect during the first ROM CPU cycle whether the ROM is on the peripheral bus or on the local bus, and the MC/PBHB will then either pass the signal to the peripheral bus if that is where the ROM is located, or will not pass it--in which case the local bus controller will take over and read the ROM which must be located on the local bus since it is not located on the peripheral bus.

Computer system for detecting and accessing BIOS ROM on the local or

Computer system for detecting and accessing BIOS ROM on local bus

Computer system and method of operation thereof wherein a BIOS ROM can

Methods and system for memory control in a computer system having a store-in cache. In response to main memory read or write requests from a secondary processor, data is transferred into a buffer during a snoop cycle to the store-in cache. The data in the buffer is merged with write-back data from the store-in cache in a write operation. Data is provided directly from the buffer to the secondary processor and to main memory in a read operation. The buffer can be placed on a memory controller of the computer system. A second store-in cache can also be used for main memory transfers.

Methods and systems for merging data during cache checking and

Methods and system for merging data during cache checking and write-back

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Waterville, VT, United States of America

William R Greer