Intel Corporation

William R Greene

Hong Wang

Dale Calvin Morris

Gary N Hammond

Jonathan Kent Ross

Perry H Wang

John P Shen

Kushagra V Vaid

John V Lovelace

Amy L Santoni

David J O'Shea

Steve Shih-wei Liao

Piyush N Desai

Todd A Schelling

Amy L O'Donnell

Bassam N Elkhoury

Craig M Valine

Hin L Leung

Ashok N Seshadri

Anthony N Mah

Ravi K Chandran

Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.

Performance in a virtualization architecture with a processor abstraction layer

A virtual multithreading hardware mechanism provides multi-threading on a single-threaded processor. Thread switches are triggered by user-defined triggers. Synchronous triggers may be defined in the form of special trigger instructions. Asynchronous triggers may be defined via special marking instructions that identify an asynchronous trigger condition. The asynchronous trigger condition may be based on a plurality of atomic processor events. Minimal context information, such as only an instruction pointer address, is maintained by the hardware upon a thread switch. In contrast to traditional simultaneous multithreading schemes, the virtual multithreading hardware provides thread switches that are transparent to an operating system and that may be performed without operating system intervention.

User-programmable low-overhead multithreading

One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

Firmware architecture supporting safe updates and multiple processor types

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Fort Collins, CO, United States of America

William R Greene