Bolt Beranek and Newman Inc.

Cisco Technology, Inc.

William R Crowther

Philip P Carvey

Randall David Rettberg

William P Brandt

Stanley A Lackey, Jr

William B Barker

Frank E Heart

Severo M Ornstein

Daniel C Tappan

C Philip Levin

Technique for connecting cards of a distributed network switch

The classifier device disclosed herein analyzes message headers of the type which comprise a sequence of bit groups presented successively. The device employs a read/write memory for storing at a multiplicity of addresses, an alterable parse graph of instructions. The parse graph instructions include node instructions which comprise opcodes in association with respective next address characterizing data and terminator instructions which comprise identifying data for previously characterized header types. A logical processor responds to a node instruction read from memory either by initiating another memory read at a next address which, given the current state of the processor, is determinable from the current node instruction and the current header bit group or by outputting data indicating recognition failure if no next address is determinable. The logical processor responds to a terminator instruction by outputting respective header identifying data. Accordingly, for a previously characterized header type, a corresponding pattern of node instruction and a terminator instruction can be written into memory thereby enabling the device to identify the respective header type in a time which is essentially proportional to the length of the header and thus also to the time of presentation of the header. The parse graph can be updated dynamically during the operation of the classifier.

Message header classifier

In parallel processing computational apparatus, a switching network employing both routing switch elements and concentrator elements efficiently couples bit serial messages from a multiplicity of processors to a multiplicity of memory modules. The apparatus operates in a highly synchronous mode in which all processors issue memory requests only at essentially the same predetermined time within a frame interval encompassing a predetermined substantial number of clock periods. The routing switch elements and concentrator elements incorporate circuitry for comparing the addresses of requests which may be blocked at any element with requests which get through and, if the addresses are the same, returning the memory response to all processors seeking the same memory location.

Memory accessing switch network

Computer apparatus which employs a plurality of processing units, a memory unit, and a communication unit, each of the units including a data transfer bus. A bus coupler is provided between each pair of units of differing type to form a distributed data communications network. An addressable, passive task register is associated with one of the units for communication through the couplers and is adapted to register a task priority value associated with a task request, the register being readable by any one of the processor units to obtain the highest priority value registry.

Multiprocessor computer apparatus employing distributed communications

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Lincoln, MA, United States of America

William R Crowther