Cadence Design Systems, Inc.

Rambus Inc.

Infineon Technologies Ag

Northrop Grumman Systems Corporation

G-2 Networks, Inc.

William Pierce Evans

Eric Harris Naviasky

Stephen T Williams

Adrian Luigi Leuciuc

Anthony Caviglia

Scott David Huss

Hamid Partovi

Eric Naviasky

Hao Tang

Patrick G Farrell

Alberto Baldisserotto

Hugh Thompson

Michael Casas

C Thomas Gray

Luca Ravezzi

John Ebner

A time to digital converter with a successive approximation architecture () and a method thereof is provided. The time to digital converter () includes successive approximation analog to digital converter circuitry () configured for converting the differential voltage established in the digital to analog converter () of the successive approximation analog to digital converter circuitry () to a digital representation thereof, where the differential voltage corresponds to a measured time period representing a time difference between receipt of leading edges of two signals. Time to digital converter () may incorporate a current switching unit (') having a plurality of current switching circuits (--) arranged in parallel to increase the precision of digital time output of time to digital converter (). The plurality of current switching circuits (--) can be selectively enabled to alter the sensitivity of the time to digital converter ().

Time to digital converter with successive approximation architecture

A system and method are provided for the detection and correction of metastability errors in a successive approximation analog to digital converter (ADC). The successive approximation ADC () includes a comparator unit () that includes a NAND gate circuit () that outputs a comp_rdy_n signal when the comparator () has latched a result. ADC () includes a metastability detection and correction circuit () that includes a first logic circuit () that monitors the comp_rdy_n signal and detects a metastable event if that signal is not received within a portion of a conversion time period of the ADC. Responsive to detection of a metastable event, a second logic circuit () generates a correct conversion code at the output of the ADC. If no metastable event is detected during a conversion cycle of the ADC, the second logic circuit () outputs the conversion codes determined by the comparator ().

Metastability error detection and correction system and method for successive approximation analog-to-digital converters

An analog to digital converting system () includes an analog to digital converter (ADC) circuit that is formed by a plurality of parallel ADCs (ADCADC N) for continuous sequential processing of an input analog voltage signal. Each of the ADCs is a type that employs a capacitor digital to analog converter (DAC) () therein. The system further includes a sample and hold circuit () coupled to the parallel ADCs by a conductive interconnect wiring pattern (). The sample and hold circuit includes a sampling switch () and a hold capacitance formed by the parallel combination of a hold capacitor () and the distributed parasitic capacitance () of the conductive interconnect wiring pattern (). During the hold phase of the sample and hold circuit, charge is redistributed from the hold capacitance to all of the capacitors () of the capacitor DAC, which serve as a secondary hold capacitance.

Parallel analog to digital converter architecture with charge redistribution and method thereof

A system and method are provided for level shifting signals generated by an electronic circuit with selectively controlled frequency response. A first circuit portion defines a primary path for a signal within an upper region of a predefined signal frequency range, and includes a first capacitor unit establishing a voltage level shift for a signal passing therethrough. A second circuit portion selectively defines a secondary path bypassing the primary path for a signal within a lower region of the predefined signal frequency range, and includes a switched capacitive section disposed in parallel across the first capacitor unit to establish a voltage level shift for the signal passing therethrough. A second capacitor unit charges substantially to a predetermined shift voltage in a charging phase and couples to the first capacitor unit during a transfer phase. An attenuation adjust unit adjustably augments a parasitic capacitance of the first or second circuit portion.

System and method for level shifting signals with adjustably controlled frequency response

A system and method are provided for adaptively controlling timing in SAR ADC of a sampled analog signal within a conversion period. A state machine maintains a set of SAR states including a sampling state and a plurality of bit conversion states. A reference generator generates a quantization level reference for each of the bit conversion states within a parametric settling time thereof. A comparator compares the sampled analog signal with the quantization level reference over a parametric propagation time for determining a hit value for each hit conversion state. A clock generator adaptively defines signals for clocking the state machine and comparator for each SAR state, thereby adaptively delaying bit determination in each bit conversion state by an integration period not less than the settling time, while adaptively delaying quantization level reference generation for a next bit conversion state by a regeneration period not less than the propagation time.

System and method for adaptive timing control of successive approximation analog-to-digital conversion

A CMOS phase interpolation system comprises a capacitive integration unit coupled to a charge node and a plurality of selectively enabled current source units operably coupled to the charge node. The current source units each include: a charging segment; a discharging segment; and, a switching segment operable responsive to at least one periodic reference signal to selectively couple the charging and discharging segments to the charge node for alternatively charging and discharging the capacitive integration unit therethrough. The current source units are selectively enabled in predetermined combinations to uniquely define an output waveform at the charge node. An output conditioning unit coupled to the charge node generates a recovered periodic signal based on the output waveform. In certain applications, a duty cycle correction unit coupled to feed back from the output node adaptively biases a charging segment current of each enabled current source unit, responsive to the recovered periodic signal.

CMOS phase interpolation system

A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Dual loop clock recovery circuit

The serial interface operable, for example, to facilitate high speed differential data transfer between integrated circuits provides level shifting of an incoming data signal using a switched capacitor technique which level shifts the common mode voltage with minimal attenuation and minimal reduction of bandwidths. The serial interface also includes a DC offset correction loop of the input data receiver path. The level shifting circuit operates by sensing the incoming common mode voltage of a differential data signal with a resistor divider and sampling the difference between the measured input common mode voltage and desired input differential voltages generated by a differential DAC in the DC offset correction loop on two small capacitors. The small capacitors are switched across larger in-signal-path capacitors cyclically, so that over time a charge will build up to give the desired level shift to shift the common mode voltage of the incoming signal to the level tolerable by low voltage high speed transistors in the receiving integrated circuit.

System and method for level translation in serial data interface

A multiple-input follower amplifier is coupled through a configuration of switching devices to an upper reference voltage at a number of its inputs and to a lower reference voltage at the remaining number of its inputs to form a voltage interpolator. The output of the voltage interpolator is a voltage between the upper and lower reference voltages proportional to the number of inputs coupled to each reference voltage. The voltage interpolator may be constructed so that the interpolated voltage may be selected through a reduced number of signal lines, such as by a row/column selection scheme. A voltage reference circuit providing the upper and lower reference voltages may also implement a row/column selection mechanism, thereby allowing a decoding scheme common to both a voltage reference circuit and a voltage interpolator in a digital-to-analog converter.

Voltage interpolation in digital-to-analog signal conversion

A clock signal can be synthesized by performing a clock and data recovery (CDR) operation on a potentially noisy clock source signal which has a known transition density. The CDR operation produces a desired clock signal in response to the clock source signal. In order to reduce crosstalk between plesiochronous receive and transmit clock domains of a serial data transceiver, a single common PLL is used both to recover the receive clock from the received data and to synthesize the transmit clock from a potentially noisy transmit clock source signal.

CDR-based clock synthesis

The present invention provides a method and mechanism for regenerating the clock signal and recovering the data of a serial bit data stream. According to an embodiment, a circuit for recovering data from a serial bit stream may include a de-serializer configured for reclocking the serial bit stream using at least one reclocking signal, having a frequency with a phase, and de-serializing the serial bit stream into at least two bit streams. The circuit may further include a clock recovery loop filter having a second order filter coupled with the deserializer. The clock recovery loop filter may be configured for determining whether the de-serializer is reclocking the serial bit data stream at an optimum location and for generating at least one control signal to adjust the phase of the frequency of the at least one reclocking signal if the de-serializer is not reclocking the serial bit data stream at the optimum location. The circuit may also include a phase interpolator coupled with the clock recovery loop filter and the de-serializer, configured for generating the at least one reclocking signal in accordance with the at least one control signal.

Clock recovery circuit with second order digital filter

A circuit and method for driving the output signal, having a common-mode voltage and an output swing, of an integrated circuit. In accordance with an aspect of an embodiment of the present invention, a first power supply provides the termination voltage for the output signal and a second power supply provides the power to set the common mode voltage. In accordance with another aspect, the common-mode voltage and the output swing are programmable.

Output driver for an integrated circuit

A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.

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Catonsville, MD, United States of America

William Pierce Evans