Intel Corporation

William Penner

Tsvika Kurts

Shay Gueron

Ittai Anati

Hermann Gartler

Boris Dolgunov

Elias Khoury

Vladislav Mladentsev

Maor Kima

Eran Shlomo

David W Grawrock

Kevin Safford

Bruce Querbach

Larisa Novakovsky

Yoni Aizik

Tieyu Zheng

Hisham Shafi

Keshavan K Tiruvallur

Mark B Trobough

Chinna B Prudvi

Vui Yong Liew

Ashok N Kabadi

Samie B Samaan

Keith A Drescher

Mukesh Kataria

Jay Joseph Nejedlo

Lyle E Cool

James J Grealish

Russell J Wunderlich

Brian Meyer

Abhijit Davare

Priyadarsan Patra

Michael J St Clair

Ki W Yoon

Ridvan A Sahan

Rahima K Mohammed

Yuen Tat Lee

John L Baudrexl

Kapila B Udawatta

Arun R Ramadorai

Wee Hoo Cheah

Kip C Killpack

Kyle Markley

Christian E Iovin

Loren James McConnell

Selvakumar Raja Gopal

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Sanjay S Salem

David C Florey

Travis K Goff

Evan J Halprin

Jiun Long Foo

Systems and techniques of the present disclosure may provide remote debugging of an integrated circuit (IC) device while preventing unauthorized access of device intellectual property (IP). A system may include an IC device that generates an encrypted session key and an interface that enables communication between the IC device and a remote debugging site. The interface may enable the IC device to send the encrypted the encrypted session key to initiate a remote debug process, receive an acknowledgement from the remote debugging session, and authenticate the acknowledgement. Further, the interface may enable to the IC device to initiate a secure debug session between the IC device and the remote debugging site.

Systems and methods for intellectual property-secured, remote debugging

Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

Supporting hang detection and data recovery in microprocessor systems

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

Growing community of inventors

Olympia, WA, United States of America

William Penner