Ncr Corporation

Gould Inc.

Teradata Us, Inc.

Encore Computer U.s., Inc.

William P Ward

Donald K Lauffer

Douglas Paul Brown

John Mark Morris

P Keith Muller

Rocky M Young

Carson T Schmidt

George B Gillow

Wayne J Lewis

Scott E Gnau

Royston L Smith

Douglas R Beard

James H Thomas

A virtual regulator monitors and manages a plurality of database systems in a domain. Each of the database systems is tuned for a particular type of workload, and the virtual regulator or multiple virtual regulators running in parallel routes a set of one or more queries to a particular database system within the domain based on a cost function for each database system.

Dynamic query and step routing between systems tuned for different objectives

A disk drive having a single drive motor and multiple platters that incorporates two discrete data paths, actuators and heads to the disk platters. Utilizing the economy of very large capacity disk platters, two or more disk drives can be created within a single physical enclosure. These two disks will be share many common parts such as the drive enclosure and spindle motor, but will have the performance and appearance to the system as two or more independent disks. Instead of having one actuator arm, the virtual disks will have two or more actuator arms and two or more sets of digital electronics. The storage on all the platters is divided up among the actuators so that no storage location is shared, but all the actuators will operate concurrently. Each actuator will have exclusive use of a subset of the data storage. Disks normally only have one actuator connected to multiple heads, at least one per surface, which only allow a single data seek and data transfer at a time. The virtual disks will have two or more actuators, one for each virtual disk, improving performance for the capacity of the platters through concurrent data seeks and transfers to different data areas.

Multiple disks in a single disk package

A system comprises a plurality of memory controllers connected to a memory bus. Each memory controller is able to generate memory requests on the memory bus according to a predetermined priority scheme. One priority scheme is a time slot priority scheme, and another priority scheme is a request-select priority scheme. The plurality of memory controllers are able to monitor memory requests generated by another memory controller in performing memory-related actions, such as memory requests (read or write), read-modify-write transaction, and cache coherency actions. In one arrangement, the memory bus is a Rambus channel.

Providing multiple memory controllers on a memory bus

An advance polling bus arbiter includes a priority selector for selecting during a polling cycle a highest priority source system unit which is seeking access to a system bus. Bus grant logic sends the highest priority source system a bus grant signal which indicates that the selected system unit can make a transfer during the next cycle. An advance link logic unit compares a target bus address received from the selected system unit to a local bus address and simultaneously signals an intersystem bus link of an impending intersystem transfer while the source system unit is receiving its bus grant signal.

Advance polling bus arbiter for use in multiple bus system

An improved system bus structure for versatile use in various digital computer architecture configurations, particularly those of mini-supercomputers, and, designed to support high speed, high reliability, parallel processing of bi-directional signal transfers in a multi-port and multiple central processor unit (CPU) communication environment as between system bus units or devices. The system bus structure may be sized for a compact encasement and may carry as many as 129 simultaneous signals to and from various units connected to it. The system bus structure includes enabling structure for a centralized arbitration system, a centralized clock and synchronized transfer system, a centralized transfer monitor, a centralized parity error assessor and signalling system including transfer termination, and, a memory/inter-system inhibit system.

Bus structure for overlapped data transfer

A cache memory includes an address modification circuit for operation during a cache block fetch sequence. The address modification circuit is connected to a polling circuit which receives a first word address from other portions of the cache memory connected to an instruction unit. The polling circuit tests whether a memory module storing the first word is free to make a data return transfer to the cache memory. When the memory module indicates that it is inhibited from making the data return to the cache memory, the address modification circuit selects in order of priority the next word in a cache block to be fetched and polls a memory module storing the next word. Word address selection and polling continues until a free memory module responds or until all words in the cache block have been fetched from main memory.

Cache memory address modifier for dynamic alteration of cache block

A register circuit capable of use in various components of a computer. The register circuit includes two registers and logic circuitry that enables plural data buses to be selectively connected in various configurations to the data inputs and outputs of the registers. In an embodiment showing the register circuit constructed using emitter coupled logic, a clocking circuit generates clocking signals for selecting the data buses to be connected to the input of each register. Each register comprises plural master-slave flip-flops which receive the clocking signals from the clocking circuit and operatively connect the flip-flops to the selected bus or buses in response to such signals.

Reconfigurable register and logic circuitry device for selective

A data processing system implemented in LSI includes error detection and correction (EDC) circuits operating either in an error correction code (ECC) mode by generating ECC parity bits, or a byte parity mode by generating or checking byte parity bits. Each EDC circuit is identical and is capable of delivering identical control signals to byte sliced memory interface chips for purposes of error correction. The EDC circuits may be used individually with a 32 bit data bus or may be combined for use with a 64 bit data bus.

Data processing system having error detection and correction circuits

A data storage system for storing multilevel, non-binary data includes a charge coupled device (CCD) shift register and a detection circuit for detecting the data level represented by the charge or signal within each cell location of the CCD shift register. The detection circuit includes a sense amplifier for comparing the signals from two adjacent cell locations, with one signal representing a known data level. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors cause the output of an incrementing digital-to-analog converter to be added to one of the signals prior to comparison. The output of the sense amplifier is provided to a flip-flop, which controls the switching transistors. The outputs of the sense amplifier and flip-flop are connected to an EXCLUSIVE NOR gate, whose output enables an up/down counter, which in turn provides the detected data level.

Data storage system for storing multilevel signals

A data storage system having a charge coupled device (CCD) shift register and a detection circuit for detecting the binary value represented by the charge level or signal within each cell location of the CCD shift register. The detection circuit includes a sense amplifier for comparing the signals from two adjacent cell locations, with one signal representing a known binary value. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors cause an adjustment voltage to be added to one of the signals prior to comparison. The output of the sense amplifier is provided to a flip-flop, which in turn has an output initially set at the known binary value and which controls the switching transistors.

Data storage system

A high density memory system is formed by reducing the number of electrical conductors that are needed to connect individual memory devices into an operable memory system. The reduction is accomplished by serially reading and writing data from and into selected memory elements on one function conductor while eliminating the need for additional control conductors by causing the state of the signal on a clock conductor as compared to the state of the signal on the function conductor at selected times to control the operating mode of the memory system.

High density memory device

A coding technique and circuit implementation for reducing the number of electrical contacts to a memory device, which memory device is configured as part of a monolithic structure. Memory selection is achieved by changing at least one characteristic of a clock signal, such as pulse width. A read or write operation is selected by a mode selector, the level of which is determined by the level of the signal on a function contact when memory selection is achieved.

Minimum pin memory device

A circuit for reducing the number of external pins or terminals on a memory device includes a counter circuit which periodically causes the signal on a first external pin to be provided to the power terminal of an internal power supply within the memory device and, at the same time, causes the ground level signal on a second external pin to be provided to the ground terminal of the internal power supply. At other times during the receipt of signals on the two external pins, the signal on the first pin provides both memory select and clocking functions and the signal on the second pin provides memory mode select, address, and data input and output functions.

Memory device having a minimum number of pins

A memory device includes a circuit for reducing the number of pins or external terminals on the memory device. A threshold detector within the circuit detects the difference in voltage between signals applied at two external pins. A clocking signal at one pin provides, in addition to a synchronizing function, a memory device select function, and a signal at the other pin provides memory mode select as well as memory address, data input and data output functions. Switching transistors controlled by the output of the threshold detector connect the external pins to the power and ground terminals of an internal power supply so that the signals at the two external pins also provide the power and ground signals to the memory device.

Memory device having a reduced number of pins

A microprogrammed processor having a bit-addressable scratch pad memory with variable length operands and a method of operation which increase processor operating speed, permit use of simpler interpretive firmware, and require a reduced amount of firmware memory than prior microprogrammed processors. Microinstructions each including a six bit op code field and first and second five bit address fields are stored in a high speed firmware memory. The two address fields are transferred to address inputs of a dual port descriptor memory which stores descriptors. Two descriptors are simultaneously fetched from locations of the descriptor memory determined by the first and second address fields of the microinstruction. Each descriptor includes an address field which defines a location of the least significant bit of an operand in the scratch pad memory and a length field which defines the length of that operand. Two operands or partial operands are fetched from the scratch pad memory and transferred to a rotator circuit which automatically aligns the fetched operand to an arithmetic and logic unit which performs iterative and fractional operations. The disclosed system and method permit interpretation of virtual instructions without utilizing additional firmware subroutines to accomplish shifting or masking of variable length operands or to perform iterative operations or carry safe operations involving the operands to align them with fixed width hardware of the processor.

Growing community of inventors

Poway, CA, United States of America

William P Ward