Discovision Associates

Rolls-royce Corporation

Other

Stmicroelectronics Gmbh

Intel Corporation

Picochip Limited

Picochips Design Limited

William P Robbins

Adrian Philip Wise

Martin William Sotheran

Helen Rosemary Finch

Anthony Mark Jones

Anthony Peter Claydon

Kevin J Boyd

Mark Barnes

Andrew Peter Kuligowski

Nicholas Birch

David Andrew Barnes

Anthony M Jones

Donald William Patterson

Anthony Peter J Claydon

Colin Smith

Kevin D Dewar

Richard J Gammack

Charles Dunlop MacFarlane

Anthony Peter John Claydon

Gajinder Singh Panesar

Thomas Foxcroft

Richard James Thomas

Andrew Duller

Fabrizio Simone Rovati

Howard Gurney

Andrew MacCormack

Andrew William George Duller

Kevin Douglas Dewar

Michael Davison

Andrew Kuligowski

Simon Howell

David Wilkins

Anthony Peter J Clayton

Olfat Younis

Anothy Peter Claydon

Peter Claydon

Alex Orr

Donald W Walker Patterson

A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimized for use in signal processing operations, in that the multiple execution units of the processor are divided into groups which do not place significant restrictions on the desirable uses of the processor, because it has been determined that, in signal processing applications, it is not usually necessary for certain execution units to operate simultaneously. These execution units can therefore be grouped together, in such a way that only one of them can operate at a particular time, without significantly impacting on the operation of the device. An array is formed from multiple interconnected processors of this type.

Processor architecture for processing variable length instruction words

There is provided a method for routing a plurality of signals in a processor array, the processor array comprising a plurality of processor elements interconnected by a network of switches, each signal having a respective source processor element and at least one destination processor element in the processor array, the method comprising (i) identifying a signal from the plurality of unrouted signals to route; (ii) identifying a candidate route from the source processor element to the destination processor element, the candidate route using a first plurality of switches; (iii) evaluating the candidate route by determining whether there are offset values that allow the signal to be routed through the first plurality of switches; and (iv) attempting to route the signal using one of the offset values identified in step (iii).

Signal routing in processor arrays

Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.

Communications in a processor array

A rotor such as a blisk B is balanced by determining the extent of any static or couple unbalance when the rotor is rotated about a test axis X while supported at a location surfaceat which the rotor is supported in normal use. The location surfaceis then modified, for example by removing material in a final machining operation, to eliminate the unbalance. For example the swash of the surfacemay be altered and/or modification may be made to other location features () in order to cause the rotor to rotate, in normal operation, about an axis which is eccentric to the test axis X.

Rotor unbalance correction

The present invention relates to the demultiplexing of a digital data stream in a receiver so as to retain only those parts of the digital data stream required by the receiver. Such demultiplexing is particularly useful when applied to a receiver circuit in a television system having a digital set-top-box. A memory in the receiver stores packet identifiers of data packets required by the receiver, which are stored in the memory under the control of a first control circuit. A second control circuit extracts packet identifiers from incoming data packets in an input digital data stream. A third control circuit receives the extracted packet identifier and determines whether this matches one of the packet identifiers stored in the memory. A match signal is set by the third control circuit to the second control circuit responsive to a match. The second control circuit demultiplexes the input data packet responsive to the match signal.

Digital receiver demultiplexer

A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number. A token decode circuit positioned in certain of the stages recognizes certain of the tokens as control tokens pertinent to that stage and passes unrecognized control tokens to a succeeding stage. A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token. Methods relating to the decoder and decompression system include processing steps relating thereto.

Multistandard video decoder and decompression system for processing encoded bit streams including start code detection and methods relating thereto

An array of processing elements can incorporate a degree of redundancy. Specifically, the array includes one or more spare, or redundant, rows of array elements, in addition to the number required to implement the intended function or functions of the device. If a defect occurs in one of the processors in the device, then the entire row which includes that defective processor is not used, and is replaced by a spare row.

Processor array

A circuit and method for demultiplexing in a receiver a digital data stream including at least two types of data. In one particular application, such a receiver is used in a television system having a digital set-top-box receiver. A first control circuit extracts a packet identifier from an input data packet in the digital data stream, and generates a signal in dependence on whether the input data packet is of the first or second type. Sets of information associated with the first types of data packets and required by the receiver are stored in a memory under the control of a second control circuit. A third control circuit, responsive to receipt of the first type of input data packet, determines whether at least part of the input data packet matches the stored sets of information, and sets a match signal responsive thereto.

Flexible filtering

Multistandard video decoder and decompression system for processing encoded bit streams including a video formatter and methods relating thereto

A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream, A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token.

Multistandard video decoder and decompression system for processing encoded bit streams including a reconfigurable processing stage and methods relating thereto

Multistandard video decoder and decompression system for processing encoded bit streams including start codes and methods relating thereto

A method of balancing a rotor (), the said method comprising the steps of determining the position of the center of mass of a rotor () to be balanced prior to the rotor () being machined to its final dimensions, and machining the rotor () to its final dimensions by removing material substantially along the length of the rotor (). The material is removed in the direction of its axis such that the center of mass of the rotor is adjusted to be substantially co-incident with its axis of rotation ().

Rotor balancing

A method of balancing a rotary device () for balanced rotational operation when connected to a drive shaft () by a flexible coupling (). The method comprises the steps of connecting a drive shaft simulator () to a rotary device () and, rotating the said device () to simulate drive shaft unbalance due to misalignment of the rotary device () and the drive shaft () being simulated when the drive shaft () and rotary device () are connected together.

Rotor balancing and drive shaft simulator therefor

A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number. A token decode circuit positioned in certain of the stages recognizes certain of the tokens as control tokens pertinent to that stage and passes unrecognized control tokens to a succeeding stage. A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token. Methods relating to the decoder and decompression system include processing steps relating thereto

Multistandard video decoder and decompression system for processing encoded bit streams including pipeline processing and methods relating thereto

Multistandard video decoder and decompression system for processing encoded bit streams including a decoder with token generator and methods relating thereto

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Cam, United Kingdom

William P Robbins