Raytheon Company

Hughes Aircraft Company

Hughes Electronics Corporation

William P Posey

Howard S Nussbaum

Stephen D Taylor

Steve I Hsu

William Tin Wun Shih

Gopal Raghavan

Benjamin Felder

Wade J Stone

Kikuo Ichiroku

Douglas Edward Lapp

Mark Youhanaie

Joseph J Jensen

A method for implementing an object based vulnerability model includes identifying each component in an information system and annotating such component in a database; decomposing each component into major functional objects and annotating each object in a database; identifying actions an attacker could take to modify a behavior of the functional objects in the information system and annotating such actions in a database; capturing a trust score and a trustworthiness score for each object and annotating the trust score and the trustworthiness score in the database; assessing each action on the structure, state, and inputs of each functional object to determine if an interaction exists and annotating the interaction existence in the database; and applying preventive and reactive countermeasures accordingly.

Method for objectively and completely indentifying system residual vulnerabilities

A method for developing an information system specification includes: performing, from a design specification for an information system having a functional and structural component, an information assurance component and an anti-tamper component, a trust analysis identifying which components of the information system the information system must trust to enforce a security policy and providing a trust score; performing for each system element in the information system a trustworthiness assessment and providing a trustworthiness score; performing mitigation to reduce a trust gap as determined from the trust score and the trustworthiness score; performing a vulnerability assessment to identify residual vulnerabilities determined from the vulnerability assessment; mitigating the residual vulnerabilities by designing preventive and reactive countermeasures to reduce the number of residual vulnerabilities; designing and applying anti-tamper techniques to cyber RCPI to ensure countermeasure effectiveness; assessing the countermeasures applied to the information system; assessing the security risk associated with the remaining residual vulnerabilities to determine if such residual vulnerabilities are acceptable to protect critical data and technology in the information system; and changing and updating system requirements for the information system as required by the designing preventive and reactive countermeasures step and the designing and applying anti-tamper techniques step.

Method for systematically and objectively assessing system security risk

A technique is described for providing a pulsed radar exciter signal, in a radar exciter including a direct digital synthesizer (DDS). The DDS is reset pulse-to-pulse to provide a pulsed DDS signal having pulse-to-pulse phase discontinuities due to the resetting of the DDS. The phase of the pulsed DDS signal can be shifted pulse-to-pulse by a phase shift that is held constant over a pulse to correct the pulse-to-pulse phasing of the DDS signal. A discrete phase modulator can provide the phase shift. The phase of the pulsed DDS signal can be shifted pulse-to-pulse by an additional phase shift which is a linear phase sequence from pulse-to-pulse, or by an additional phase shift which is a quadratic phase sequence from pulse-to-pulse to produce a ranging waveform.

DDS spur mitigation in a high performance radar exciter

An antenna array system with dynamic signal routing to a set of receivers. A monopulse electronically scanned antenna (ESA) has a plurality of antenna elements divided into subarrays. ESA beam steering phase shifters are associated with the respective subarrays of antenna elements, such that the output signals from the respective antenna elements associated with the respective quadrants are phase shifted and summed to provide respective subarray signals. A monopulse network responsive to the subarray signals provides monopulse outputs to a set of receivers. A beam steering controller provides phase shift commands to the ESA phase shifters to set the phase shift associated with the respective phase shifters of the subarrays. The controller commands the ESA phase shifters to modulate the phase shift of selected quadrants. The phase shifts associated with the subarrays are selectively set to either 0 or 180 degrees relative to one of the subarrays by adding the desired subarray phase shift (0 or 180 degrees) to the beam steering phase command at each element. This produces the main array signals. By setting the subarrays's phase shifts, the main array signals are appropriately steered to the desired receivers. The dynamic signal routing can also be used with non-electronically scanned systems.

Dynamic signal routing in electronically scanned antenna systems

Processing apparatus is provided that directly samples and quantizes a complex envelope of a bandlimited waveform centered at a predetermined carrier frequency. An oversampling delta-sigma modulator 1 samples and quantizes the input signal to a single bit data stream. A serial-to-parallel converter converts the single bit data stream into a parallel bit stream. A digital decimation filter digitally filters the parallel bit stream to produce an estimate of the baseband in-phase and quadrature components of the input signal. In-phase and quadrature video filters generate in-phase and quadrature samples that are output from the analog signal converter. A controller 26 and a plurality of digital-to-analog converters 25 are used to center noise shaping nulls of the delta-sigma modulator around the carrier frequency. The controller sets the spacing between nulls of the serial-to-parallel converter to maximize the signal-to-noise ratio of the analog signal. The controller controls the decimation filter to set the sample times of thereof to sample the carrier in quadrature so that the coefficients are programmed to form a bandpass filter at the carrier frequency and programs the coefficients of the video filters to form bandpass filters at the decimated carrier frequency.

Flexible and programmable delta-sigma analog signal converter

A phase shifter using digital counters allows extremely accurate phase shifts. In a parallel circuit arrangement of a number of basic phase shift units, which each includes a dual modulus counter and phase control circuitry for controlling the counter modulus, the outputs of several units are combined in parallel. With the divider ratios of all the dividers of the units consisting of roots of pairwise relatively prime numbers, the total number of phase states is equal to the multiplication of its divider ratios.

Digital frequency divider phase shifter

Discrete phase modulation for modulating the transmit and receive radar signal waveforms in order to control distortion. The signal is modulated by discrete phases which change from pulse-to-pulse. A digital frequency division circuit accurately generates the modulation signals, and allows the discrete phases to be generated with precise accuracy. The discrete phase changes can be a quadratic phase progression for target Doppler and range detection.

Discrete phase modulator

A phase shifter that employs digital circuitry to achieve arbitrarily fine phase control of reference signals at frequencies extending to the Gigahertz region. The phase shifter includes a cascade of identical phase shift units that provide progressively finer phase control resolution over a full 360 degree range. The phase precision is set by the number of stages used.

Precision digital phase shifter

A precision digital phase shift element for achieving precise phase shift of an input pulse train signal. The output is a pulse train at a frequency equal to the input signal frequency divided by N, and having N equally spaced phase states. The relative phase state of the output signal is reliably controlled by selective deletion of pulses from the input signal pulse train. The selective deletion can be achieved by selectively gating the input pulse train, or by use of a dual modulus frequency divider circuit.

Precision digital phase shift element

A modulation is applied to a received radar signal prior to analog-to-digital (A/D) conversion, and is removed subsequent to A/D conversion, to mitigate the effects of nonlinear receiver harmonic distortions and receiver spurious responses. The received target and clutter signals pass unchanged through the receiver to the digital signal processing. Harmonic distortion products and spurious responses introduced in the receiver after the modulation has been applied are distorted by the demodulation signal. By proper selection of the modulation waveform, coherent harmonic distortion products and spurious responses are converted to wideband noise reducing the level of interference that competes with targets in the affected Doppler filters.

System and method for radar receiver harmonic distortion and spurious

A linear predictive ADC employs a fully feed forward design to extend its dynamic range, allow greater speed of operation, achieve stable operation and eliminate a requirement for sample-and-hold circuits. A first quantizer (Qc) converts an input analog signal to a digital format, while a signal predictor (32) predicts a subsequent value of the input signal. After conversion back to analog format, the predicted signal is compared with the actual subsequent value of the input signal to produce an error signal that is converted to a digital format by a second quantizer (Qf). The digital predicted signal is fed forward and combined with the digital error signal to produce a high precision digital output. The analog error signal is preferably amplified prior to digitation to take advantage of the full bit capacity of the second quanitzer (Qf), and then digitally de-amplified back to its original scale. Digital gain and offset adjustment mechanisms (44, 50) are preferably provided to compensate for amplification/de-amplification mismatches and system offsets. The quantizers (Qc, Qf), predictor (32) and a digital register (36) that interfaces between the predictor and the output combiner (46) are clocked in a set sequence to ensure that the predicted signal from the register (36) corresponds in time to the error signal presented to the output combiner (46).

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Palos Verdes Estates, CA, United States of America

William P Posey