Crosspoint Solutions, LLC

William P Ingram, Iii

Richard Klein

Pankaj Dixit

Monta R Holzworth

Various improvements in the fabrication of an antifuse having silicon-amorphous silicon-metal layer structure are presented. Included are improved deposition techniques for the amorphous silicon layer. The improvements include steps for the fabrication of such an antifuse without the use of platinum and the resulting antifuse and contact structures.

Method of fabricating antifuses in an integrated circuit device and

An antifuse structure particularly suitable for field programmable gate arrays is presented. In most present day processes the antifuse structure is formed with a refractory metal layer, amorphous silicon layer and refractory metal layer sandwiched between two metal interconnection lines. Unprogrammed resistances of very high values, programmed resistances of very low values, short programming times and desirable programming voltages are among the advantages realized.

Antifuse circuit structure for use in a field programmable gate array

Improved method of fabricating antifuses in an integrated circuit device

An antifuse particularly suitable for submicron geometries is presented. The antifuse is formed between a silicon layer, which could be a doped region of the semiconductor substrate, an epitaxial layer or a polysilicon layer, and an upper metal interconnection layer. In contact holes in a silicon dioxide layer insulating the silicon and metal interconnection layers from each other, the antifuses have a thick refractory metal layer having a top surface approximately at the same level as the top surface of the insulating layer. Depending upon the process used to deposit the refractory metal layer, a thin adhesion layer may be located immediately below the refractory metal layer. Between the underlying silicon layer and upper interconnection layer, a thin semiconductor material layer of amorphous silicon may be located either below the refractory metal layer or above it. At its bottom, the interconnection layer also has a barrier layer to prevent any intermixing between the amorphous silicon layer and the metal interconnection layer.

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William P Ingram, Iii