Westinghouse Electric Corporation

United States of America As Represented by the Secretary of the Air Force

William P Evans

Eric H Naviasky

John R Smith

Thomas F Kelly

Daniel W Jefferies

Thomas K Lisle, Jr

Robert J McCabe

The present invention is a multimode sensor system that transmits power down a common bus coaxial cable typically using an alternating current power source. Each remote unit connected to the coaxial cable and through an isolation transformer converts the alternating current power to direct current power for an integrated circuit bus interface. The interface is connected to the sensors. The interface is externally pin programmable to provide a carrier at a frequency for a channel assigned to the remote unit. The carrier is provided by a ripple counter producing a frequency divided signal compared to a fixed reference frequency, where the result of the comparison controls a voltage controlled oscillator. When plural low frequency analog signals are to be transmitted over the common bus, an on-chip multiplexer multiplexes the signals to an off-chip, external analog-to-digital converter. The analog-to-digital converter loads an on chip parallel to serial register that applies each bit of the sampled signal serially to an on chip Manchester encoder. The encoder modifies the input voltage of the voltage controlled oscillator operating at the carrier frequency. The oscillator signal is applied to the coaxial cable. Receivers at the end of the coaxial cable are each tunable to a designated carrier frequency and each decode the respective encoded signal. If a high frequency analog signal is supplied to the voltage controlled oscillator, the carrier is modulated by the high frequency signal and the receiver demodulates the signal. The integrated circuit is arranged so that the digital circuitry is generally isolated from the analog circuitry so noise immunity is enhanced.

Common bus multinode sensor system

An analog to digital converter system is disclosed as comprising a conversion circuit operative for developing a digital output corresponding to the magnitude of an input analog signal, a calibration port arranged for receiving digital calibration data from an external source, adjustable calibration circuitry associated with the conversion circuit, and an adjustment mechanism for adjusting the calibration circuitry in response to data applied to the calibration port.

A/D converter system with error correction and calibration apparatus and

An analog-to-digital converter having error correction in the digital stages of the converter. A calibration microprocessor executes a correction value program prior to, or interspaced with, the normal operation of the converter. From either of two calibration programs, appropriate digital correction values are stored into a digital memory. The analog input signal is converted to a digital signal by a main range analog-to-digital converter, with the output of the converter addressing the memory containing the error correction values. The main range digital value is reconverted to an analog signal which is compared to the original input signal to determine the difference therebetween. This analog difference is converted to a digital signal and combined with the main range digital signal and the addressed correction values to produce the digital output signal of the conversion system.

Subranging analog-to-digital converter with digital error correction

A very high speed, high resolution analog to digital converter is detained including a subrange architecture, with the main range A/D including a digital to analog portion for producing an analog signal which can be summed with an amplified input analog signal. The summed analog signal is directed through a unity gain buffer to the subrange analog to digital converter, with the buffer isolating the high input capacitance of the subrange A/D from the summing node. The main range A/D provides a binary coded digital signal which approximates the input analog signal and which defines the most significant bits (MSB) of the digital output. The least significant bits (LSB) are had from the subrange A/D which provides at least one more bit than the number of MSB to provide overlap for forming the combined digital output signal.

Architecture for high speed analog to digital converters

An analog to digital converter (ADC) is presented which uses a calibration technique to reduce harmonic distortion in data acquisition systems. This mechanization also allows faster conversion rates than previously possible for high resolution analog-to-digital converters. This converter makes use of a subrange or 'half Flash' architecture where the subrange digital-to-analog converter (DAC) is augmented with a software calibrated DAC which removes system nonlinearities. The advantage of this system is that it allows the building of higher speed data acquisition systems with higher spurious free dynamic range than would be possible with conventional techniques. By adding the correction to the input of the subrange ADC, correction resolution can be a fraction of a quanta. A second approach using the same mathematics places at the output of the ADC a RAM or ROM look up table which linearizes the transfer function.

Harmonic distortion reduction technique for data acquistion

An improved latching-type comparator operative in a selected one of two exclusive states is disclosed. In one state, the operational state, a gain stage is rendered operative to amplify at least one intermediate current signal generated by an input stage in response to the comparison of a pair of input signals. At least one drive current signal is generated by the gain stage in response to the comparison and is buffered by a corresponding buffer stage to render both an output signal and a signal representative thereof. In the other state, a latch stage is rendered operative unresponsive to the comparison and governed by the signal representative of the output signal to sustain the drive current signal in a state to latch the output signal. A switching stage governed by at least one latch signal effects the selection between the gain and latch stages by conducting operating current exclusively from the selected stage to a constant current stage. An independent second constant current stage provides current for the input stage to maintain its operation continuously independent of the selected date of the comparator.

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Glen Burnie, MD, United States of America

William P Evans