Cisco Technology, Inc.

William P Brandt

Gary S Muntz

Kenneth H Potter

Guy Fedorkow

Jonathan Rosen

William R Crowther

An apparatus and technique configures an intermediate network node, such as an aggregation router, to implement automatic protection switching (APS) redundancy among its line cards in the event of a failure to one of those cards. The APS line card redundancy provides redundancy among a pair of line cards connected to a performance routing engine of the router. Internal APS data paths are implemented in the router through the provision of an alias logic circuit that selects packet data from one of an adjacent pair of line cards and sends identical copies of data to that adjacent pair of line cards.

Automatic protection switching line card redundancy within an intermediate network node

A mapping technique allows a forwarding engine of an intermediate node to efficiently compute a starting address within an internal packet memory (IPM) configured to hold a packet received at the node. The starting address is used by direct memory access logic to merge a trailer of the packet stored in the IPM with a modified packet header generated by the forwarding engine. However, the size of the IPM is preferably not a binary number that can be easily manipulated by the forwarding engine when computing the starting address of the packet within the IPM. Therefore, the technique automatically adjusts the starting address to map to a correct location if the address exceeds the size of the IPM, while obviating the need for the forwarding engine to consider a wrap-around condition when computing the starting address.

Mapping technique for computing addresses in a memory of an intermediate network node

A zero-delay buffer circuit includes a modified phase-locked loop (PLL) circuit configured to minimize clock skew among data output buffers of modules within a high-speed network switch system. Each module includes an application-specific integrated circuit (ASIC) chip that contains the modified PLL circuit; circuitry inserted within a feedback loop of the PLL is representative of a clock distribution tree that is common to the output buffers of the chip. The absolute delay of that tree typically differs among the ASICs because of process, voltage and temperature variations within the system. The circuitry inserted within the feedback loop effectively compensates for the absolute delay of the common distribution tree circuit components.

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Groton, MA, United States of America

William P Brandt