International Business Machines Corporation

Transitive Limited

William Owen Lovett

Alexander Barraclough Brown

David Haikney

Gavin Barraclough

Alex Brown

Matthew Evans

A dynamic code translator with isoblocking uses a return trampoline having branch instructions conditioned on different isostates to optimize return address translation, by allowing the hardware to predict that the address of a future return will be the address of trampoline. An IP relative call is inserted into translated code to write the trampoline address to a target link register and a target return address stack used by the native machine to predict return addresses. If a computed subject return address matches a subject return address register value, the current isostate of the isoblock is written to an isostate register. The isostate value in the isostate register is then used to select the branch instruction in the trampoline for the true subject return address. Sufficient code area in the trampoline instruction set can be reserved for a number of compare/branch pairs which is equal to the number of available isostates.

Return address optimisation for a dynamic code translator

During program code conversion, such as in a dynamic binary translator, automatic code generation provides target codeexecutable by a target processor. Multiple instruction portsdisperse a group of instructions to functional unitsof the processor Disclosed is a mechanism of preparing an instruction groupusing a plurality of poolshaving a hierarchical structure-. Each pool represents a different overlapping subset of the issue ports. Placing an instructioninto a particular poolalso reduces vacancies in any one or more subsidiary pools in the hierarchy. In a preferred embodiment, a counter valueis associated with each poolto track vacancies. A valid instruction groupis formed by picking the placed instructionsfrom the pools. The instruction groups are generated accurately and automatically. Decoding errors and stalls are minimized or completely avoided.

Preparing instruction groups for a processor having multiple issue ports

An improved method and apparatus for performing program code conversion is provided and, more particularly, for generating improved intermediate representations for use in program code conversion. During program code conversion, a partial dead code elimination optimization technique is implemented to identify partially dead register definitions within a block of program code being translated. The partial dead code elimination is an optimization to the intermediate representation in the form of code motion for blocks of program code ending in non-computed branches or computed jumps, where target code for all dead child nodes of a partially dead register definition is prevented from being generated and target code for partially dead child nodes of a partially dead register definition is delayed from being generated until after target code is generated for all fully live child nodes for the partially dead register definition.

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Manchester, United Kingdom

William Owen Lovett