Stmicroelectronics S.a.

Stmicroelectronics (rousset) Sas

Stmicroelectronics S.r.l.

Stmicroelectronics Application Gmbh

Stmicroelectronics (grand Ouest) Sas

Stmicroelectronics (grenoble 2) Sas

William Orlando

Albert Martinez

Michel Bardouillet

Jean Nicolai

Stephan Courcambeck

Luc Wuidart

Roberto Colombo

Guido Marco Bertoni

Pierre Balthazar

Roberta Vittimani

Pierre Guillemin

Layachi Daineche

Lionel Sinegre

Stéphan Courcambeck

Sophie Gabriele

Julien Couvrand

Eric Sagnard

Pierre-Yvan Liardet

Alexandre Malherbe

Bernard Kasser

Claude Anguille

Yannick Teglia

Lydie Terras

The present description concerns an electronic system including one or a plurality of first microprocessors, a second microprocessor for securely managing first encryption keys of the first microprocessors, the second microprocessor being configured to communicate with each first microprocessor and including a first non-volatile memory having at least one second key stored therein, and for each first microprocessor, a second non-volatile memory external to the second microprocessor and containing the first keys of the first microprocessor encrypted with the second key.

Electronic system comprising a plurality of microprocessors

A method includes receiving, by a first microprocessor, a request of modification of a content of a first memory of the first microprocessor, the first memory being accessible only by the first microprocessor. The method includes accessing, by the first microprocessor, first data associated with the request and a signature generated from the first data with an asymmetric cipher algorithm. The first data and the signature are available in a second memory of a second microprocessor, and the first data is representative of a modification to be applied to the content of the first memory. The modification is representative of a modification of a set of services exposed by the first microprocessor. The method includes verifying, by the first microprocessor, authenticity of the first data based on the signature; and modifying the content of the first memory according to the first data, the modifying being conditioned by the verifying.

Modification of a memory of a secure microprocessor

A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

Method for managing a return of a product for analysis and corresponding product

A hardware monitor circuit includes an electronic control circuit coupled to a processing unit. The electronic control circuit generates multi-bit protection codes and directs operations of the hardware monitor circuit. A bus interface is coupled to an address bus of the processing unit, and the bus interface passes signals associated with a stack structure of the processing unit. The stack structure is arranged to store the multi-bit protection codes in an internal memory coupled to the processing unit. Comparators in the hardware monitor circuit are arranged to accept values from the internal memory and gating logic coupled to the comparators is arranged to generate an error signal when it detects that an address on the address bus read via the bus interface is equal to an address stored in the internal memory. Upon generating the error signal, the processing unit is placed in a secure mode.

Stack overflow protection by monitoring addresses of a stack of multi-bit protection codes

A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.

Processing system, related integrated circuit, device and method

A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.

Hardware secure module, related processing system, integrated circuit, device and method

Synchronization points are inserted into a program code to be monitored, and are associated with different branches resulting from execution of an indirect branch instruction. The synchronization points can be accessed by the monitored program code for the purpose of identifying which branch to use during execution of the indirect branch instruction of the monitored program code.

Method and tool for generating a program code configured to perform control flow checking on another program code containing instructions for indirect branching

A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.

Protection of memory areas

A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.

Memory area protection circuit

A data medium of the compact disc type may include medium areas of different types configured to define digital content, and a controllable element having two different states corresponding respectively to the two different types of areas. The controllable element may be configured to take selectively one of its states in response to a command, so as to modify in a controllable manner the content of the data medium.

Data medium of the compact disc type, in particular fitted with protection against copying, and corresponding method

A method for transmitting data between a first and a second point comprises the steps of transmitting data, from the first to the second point, together with a signature comprising bits of a first authentication code, and transmitting an acknowledgement, from the second to the first point. The length of the first authentication code is greater than the length of the signature and the first authentication code comprises hidden authentication bits. The acknowledgement is produced by using hidden authentication bits of a second authentication code presumed to be identical to the first, produced at the second point.

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Peynier, France

William Orlando