Motorola Corporation

William Oliver Mathes

Lalit O Patel

Michael P LaMacchia

Kevin Joseph Jurek

Bruce Alan Fette

A multiplexer output cell (FIG. ) controls the operation of multiplexer input cells ( ) in a multistage multiplexer according to the value of a signal select input ( ), and a state control input ( ). A signal driver ( ) having a number of logical outputs comparable to the number of stages in the multiplexer is used in conjunction with the state control signal ( ) to control the power ON/OFF state of each cell in the multiplexer. The multiplexer input and output cells ( ) which are in the signal path are set to a power ON condition, while the multiplexer input and output cells ( ) which are not in the signal path are set to a power OFF position. In this manner, only those cells which are in the signal path are powered ON, resulting in significant power savings.

Reduced power consumption multiplexer using self-decoding power down logic

A method and apparatus for controlling current flow in current sources includes a current source FET (18), a control FET (20), and a driver circuit which includes complementary logic (310). The use of complementary logic for control advantageausly allows commonly available logic functions to control the current flow in individual current sources while maintaining a substantially constant bias voltage on the gate of the current source FETs. A chip-wide bias generator can be maintained substantially constant while controlling individual current sources.

Current source and method therefor

A single event upset (SEU) sensitivity control system (42) dynamically hardens a digital circuit (48) to single event upsets. The sensitivity control system (42) includes an upset rate sensor (66) for detecting a quantity of particles (38) that cause single event upsets. A noise margin control circuit (70) is configured to adjust a noise margin (46) of the digital circuit (48) in response to the quantity of particles (38). Noise margin (46) is increased when a particle density (34) is high to decrease the sensitivity of the digital circuit (48) to single event upsets. Additionally, noise margin (46) is decreased when a particle density (36) is low to decrease the power consumption level of digital circuit (48).

Apparatus and method for dynamic hardening of a digital circuit

A method and apparatus for hardening current steering logic (CSL) to soft errors (charged particles passing through and upsetting the logic state of an integrated circuit) includes a hardened CSL circuit or cell (20), including three or more circuit cell elements (21) in parallel. The circuit cell elements (21) redundantly perform a single cell function. Each of the circuit cell elements (21) is coupled to soft error immune resistive elements (24 and 25) within a summing element (22). Current (23) is steered through the resistive elements (24 and 25) depending upon input signals (26) to each of the circuit cell elements (21). The logical output signal (27) is unaffected by a single soft error event since the majority of the total current (23) remains steered through the correct resistive element (24 or 25).

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Tempe, AZ, United States of America

William Oliver Mathes