Micron Technology Incorporated

Round Rock Research, LLC

William N Thompson

John David Porter

Larren Gene Weber

John R Wilford

J David Porter

Tom Pawlowski

An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to Vthrough parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

Latch-up prevention for memory cells

A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

Variable resistance circuit

Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.

Output data path capable of multiple data rates

An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to V through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

Method to find a value within a range using weighted subranges

Output data path having selectable data rates

A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.

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Meridian, ID, United States of America

William N Thompson