Qualcomm Incorporated

William Michael Stone

Jianwen Xu

Jonghae Kim

Periannan Chidambaram

Ryan David Lane

Giridhar Nallapati

Li-Sheng Weng

Charles David Paynter

Lizabeth Ann Keser

Jihong Choi

Christopher Healy

John Holmes

Steve Joseph Bezuk

Sun Yun

Nicholas Ka Ming Yu

Ahmer Syed

Michael James Solimando

Rajendra Pendse

Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods

A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

Package comprising integrated devices coupled through a metallization layer

An integrated circuit (IC) device that includes an IC device layer, at least one electrical connection layer located over the IC device layer, and a varying diameter via layer located over the at least one electrical connection layer. The varying diameter via layer includes (i) an interior region having a plurality of interior region vias and (ii) a perimeter region having a plurality of perimeter region vias. The plurality of interior region vias of the interior region is larger than the plurality of perimeter region vias of the perimeter region. The varying diameter via layer comprises an interior surface that is coupled to an interior surface of the at least one electrical connection layer.

Integrated circuit (IC) devices with varying diameter via layer

An integrated circuit (IC) device includes a device layer and a passivation layer, where the passivation layer has vias formed in an interior region of the passivation layer that are larger than vias formed in a perimeter region of the passivation layer. As such, a varying diameter via layer is provided. The interior region vias may be configured to reduce a risk of damage to the IC device due to tensile stress, with sizes or shapes selected based on the amount of tensile stress expected to occur during subsequent use of the IC device. The perimeter region vias may be configured to reduce a risk of damage to the IC device due to sheer stress, with sizes or shapes selected based on the amount of sheer stress expected to occur during subsequent assembly or use of the IC device. Method and apparatus examples are described for use with flip-chip dies.

A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.

Package on package (PoP) device comprising thermal interface material (TIM) in cavity of an encapsulation layer

A wafer level package device may include a molding compound that encapsulates a substrate, a back end of line and front end of line layer on the substrate and a passivation layer of a redistribution layer without encapsulating a metal layer on the passivation layer. The molding compound may eliminate sidewall chipping and cracking as well as reduce the need for back side lamination.

Wafer level package without sidewall cracking

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San Diego, CA, United States of America

William Michael Stone