Pmc-Sierra, Inc.

Pmc-Sierra US, Inc.

Maxlinear Asia Singapore Pte Ltd

Microsemi Storage Solutions (u.s.), Inc.

William Michael Lye

Hormoz Djahanshahi

Jatinder Chana

John B Groe

Anthony Eugene Zortea

Graeme Barclay Boyd

Matthew W McAdam

Mark Hiebert

John Philip Plasterer

Xun Cheng

Rod Zavari

William Dean Warner

Ognjen B Katic

Michael Ben Venditti

Claudio Gustavo Rey

Dragos Cartina

Stanley Ho

Tomas A Dusatko

Anthony B Candage

Sally Yeung

Jonathan Robert Gay

Terence K W Lau

A system and method for sampling an RF signal uses a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.

Radio frequency flash ADC circuits

An Interleaved Radio Frequency Digital-to-Analog Converter (RF DAC) suitable for use in cellular base stations and optimized to give both a wide RF tuning range and a wide RF bandwidth is disclosed. The RF DAC uses two levels of interleaving, the first providing a direct conversion path from Base Band (BB) to RF, and the second providing a variable interleaving factor through the use of summation to optimize the output bandwidth as a function of the RF center frequency. Digital Interpolation, including an arbitrary sample rate conversion filter, allows the RF DAC to operate from a wide range of possible BB sample rates and the DAC sample rate is a fixed ratio of the RF center frequency. As a result, the spurious outputs from the RF DAC are in known locations that are relatively easy to filter out, minimizing the frequency planning tasks required for a complete RF system design.

Digital-to-analog converter system and method

A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.

A system for sampling an RF signal comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.

Digital to-analog converter system and method

A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

Low-noise flexible frequency clock generation from two fixed-frequency references

Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.

System and method for synchronizing local oscillators

An apparatus comprising a scrambler having a plurality of scrambler inputs and 2N scrambler outputs, and a unary-weighted digital to analog converter (DAC) connected to scrambler to generate an analog output signal based on the 2N scrambler outputs. The scrambler has N unique scrambling stages arranged in order between the scrambler inputs and the scrambler outputs from a first scrambling stage to a last scrambling stage. Each of the N unique scrambling stages has a plurality of stage inputs and outputs, with the stage inputs of the first scrambling stage connected to the scrambler inputs, the stage outputs of each scrambling stage except the last scrambling stage connected to the stage inputs of a next scrambling stage, and the stage outputs of the last scrambling stage connected to the scrambler outputs. Each of the N unique scrambling stages is operable to pass signals at the inputs to the outputs in either an unscrambled or scrambled state under control of a control bit provided by an N-bit entropy signal. When an N+1 bit input signal is applied to the scrambler inputs and the N-bit entropy signal is randomized the analog output signal from the DAC has improved linearity compared to the analog output signal generated from a non-scrambled input, and when a test input signal is applied to the scrambler inputs and the entropy signal is swept through 2N orthogonal values the analog output signal from the DAC indicates whether a fault exists in one of the scrambler and the DAC.

Scrambler with built in test capabilities for unary DAC

A device that performs Quantization Noise-Shaping and operates at high clock rates. The device can be implemented in parallel with large parallelization factors to produce extremely high throughput. The device has two feed-forward filters that can be implemented using standard parallel Digital Signal Processing techniques. The device can be used in various systems such as Digital-to-Analog Converter (DAC) system and Fractional-N frequency synthesis systems.

Quantization noise-shaping device

A method and apparatus for interleaving high-speed, delta-sigma based over-sampled DACs. A delta-sigma modulator is decomposed into a parallel poly-phase block-filter running at a lower rate. The generated parallel digital data is then fed directly to the analog DAC output stage where it is directly combined to form the full-rate signal using a 1-hot-of-N output stage. By using a poly-phase implementation, the complexity of the high-speed parallel digital-analog timing interface is simplified, along with the timing requirements of the delta-sigma modulator which normally would have to run at the full-oversampled rate. The 1-hot-of-N signal encoding is directly generated from the parallel delta-sigma modulator, and efficiently encodes the data in such a way to minimize signal-dependent supply noise. The architecture disclosed is advantageous for the practical implementation of high-speed over-sampled DACs, such as those used in stringent wireless applications.

Interleaved digital to analog conversion

A method to look at the incoming received data on a SerDes link while running in normal operation without requiring a second receive path or any defined or repeated data patterns to be able to generate statistical eye plots both before and after any internal equalization; generate trajectory eye plots both before and after any internal equalization; estimate TED characteristics (hence also estimate SJ jitter tolerance of the link); estimate complete Channel Impulse Response (hence also estimate the S-parameters of the complete channel); and estimate the decomposed jitter of the complete channel.

Growing community of inventors

Coquitlam, Canada

William Michael Lye