Mentor Graphics Corporation

Other

William Matthew Hogan

Valeriy K Sukharev

Patrick D Gibson

Sridhar Srinivasan

John G Ferguson

Jonathan James Muirhead

Sherif Hany Riad Mohammed Mousa

Richard M Pier

Arthur J Boland

Alex Joseph Pearson

James M Paris

Aspects of the disclosed technology relate to techniques of context-aware pattern matching and processing. A circuit design is analyzed to identity circuit components of interest. Reference layout patterns that are associated with the circuit components of interest are extracted from a layout design based on the association of circuit components of the circuit design with geometric elements of the layout design. Pattern matching is performed to identify layout patterns that match the reference layout patterns. The identified layout patterns are then processed.

Context-aware pattern matching for layout processing

Aspects of the invention relate to techniques for estimating power and thermal profiles for an integrated circuit design. With various implementations of the invention, a group of devices is identified in a netlist based on information of the group of devices. The netlist may be a schematic netlist or a layout netlist extracted from a layout design. Power consumption information for the group of devices is determined based on device parameters for the group of devices and a lookup table. The determined power consumption information is then associated with layout location information. A thermal profile may then be estimated based on the power consumption information.

Estimation of power and thermal profiles

Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions for the segments of the interconnect tree are determined. Based on the current density values and the current directions, hydrostatic stress values for the nodes are computed under a steady-state condition and conservation of the conductive material within the interconnect tree. The electromigration susceptibility of the interconnect tree is then determined based on the computed hydrostatic stress values.

Determination of electromigration susceptibility based on hydrostatic stress analysis

A collaborative environment for performing physical verification processes on integrated circuit designs. Multiple physical verification results may be stored in a 'unified' results database/directory (e.g., unified at least from a user's perspective), where results from various verification processes, such as Design-Rule-Check (DRC) processes, Layout-Versus-Schematic comparison (LVS) processes, Design-For-Manufacturing (DFM) processes Optical Proximity Correction (OPC) processes, and Optical Rule Check (ORC) processes are accessible from the same style of user interface, which may be a graphical user interface. The basic abilities for design team-based interactions can be equally available to each process involved in the physical verification of an integrated circuit design.

Collaborative environment for physical verification of microdevice designs

Printed circuit board, ASIC, transistor group, or other circuit timing can be analyzed by symbolically modeling the circuit, simulating the behavior of the circuit, analyzing the behavior to catch timing violations. Routing constraints for critical traces can be made by using the analysis results as the input to a trace circuit router. Further timing verification of the printed circuit board, ASIC, transistor group, or other circuit layout may be accomplished by analyzing and modeling the interconnect delays of the traces, simulating the symbolic circuit model with the interconnect delay model, and analyzing the behavior of the circuit for timing violations.

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Lake Oswego, OR, United States of America

William Matthew Hogan