Northrop Grumman Systems Corporation

Trw Limited

William Marvin Skones

Mark Kintis

Donald R Martin

Andrew Donovan Smith

Vincent C Moretti

Craig R Talbott

Bert K Oyama

Shimen K Claxton

Ronald P Smith

Barry Ross Allen

David Joseph Brunone

Jeffrey Mark Hinrichs

Kenneth Weber

Eric L Upton

Steve Nelson

Ian Robinson

Robert R Harnden

Jasmine Upendra Patel

Paul Charles MacFalda

Brian J Rosenkoetter

Kai E Johnson

An apparatus for converting a digital input signal to an analog signal for transmission. The input signal can include more than one carrier signal. A plurality of delta-sigma modulation loop circuits are connected in an increasing order of operating frequency so as to reduce a word length of the input signal. A tuning circuit adjusts the signal frequency to a transmitting frequency for conversion to analog by a digital-to-analog converter. A first loop circuit is implemented using CMOS gates, and a second loop circuit and the tuning circuit are implemented using indium phosphide gates. The apparatus allows a high-resolution, wide-band RF multiple-carrier signal to be re-quantized to a lower-resolution signal while an acceptable signal-to-noise ratio is maintained.

Apparatus and methods for digital-to-analog conversion

Signal conversion of an input signal can be achieved by processing portions of the signal through plural parallel paths, which collectively approximate a desired infinite impulse response (IIR) filter, either alone or implemented with other signal processing functions. In one aspect, each of the paths can perform filtering, noise-shaping and/or quantization on a respective portion of the input signal to provide a corresponding representation of the respective portion of the input signal, for example, a coarser representation at a higher data rate. The corresponding representations from the parallel paths can be aggregated and further processed in a desired manner, such as conversion to an analog signal.

Conversion employing delta-sigma modulation

A receiver ( ) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver ( ) includes a specialized LNA ( ), frequency down-converter ( ) and ADC ( ) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter ( ) employs a suitable mixer ( ), BPA ( ), attenuator ( ), and transformer ( ) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC ( ). A specialized digital channelizer ( ) is included in the receiver ( ) that receives the digital signal from the ADC ( ), and separates the signals into the multiple channels. In one embodiment, the frequency down-conversion is performed in a single down-conversion process, and the ADC ( ) employs delta-sigma processing to provide digital conversion over the complete frequency band. In an alternate embodiment, the frequency down-conversion is performed in a double down-conversion process so that a less complex ADC ( ) can be used.

Wireless telecommunications multi-carrier receiver architecture

Receiver including frequency down-converter and analog-to-digital converter for a wireless telecommunication system

A receiver ( ) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver ( ) includes a specialized LNA ( ), frequency down-converter ( ) and ADC ( ) to perform the wideband signal processing while maintaining receiver performance. A specialized digital channelizer ( ) is included in the receiver ( ) that receives the digital signal from the ADC ( ), and separates the signals into the multiple channels. In one embodiment, the frequency down-conversion is performed in a single down-conversion process, and the ADC ( ) employs delta-sigma processing to provide digital conversion over the complete frequency band.

Multi-carrier receiver including an analog-to-digital converter for a wireless telecommunication system

Architecture for multi-carrier receiver

A DAC including a first switch and a second switch. The first switch receives a digital signal to be converted, and the second switch receives the digital signal delayed by one-half of a clock signal. A third switch receives a current signal from a current source and the clock signal. The third switch alternately switches the current signal to the first and second switches so that when the clock signal is positive, the current signal is applied to the first switch and when the clock signal is zero, the current signal is applied to the second switch. The first switch will output the current signal during the first half of the clock cycle to a first output or a second output, and the second switch will output the current signal during the second half of the clock cycle to the first output or the second output.

Switching DAC pulse encoding circuit

A channelizer ( ) for a multi-carrier receiver including a plurality of digital sub-band tuners (DSBTs) ( ). Each DSBT ( ) digitally filters individual carrier data bits from a digital multi-carrier data stream based on a programmable center frequency. Each DSBT ( ) further digitally filters the individual carrier data stream based on a programmable bandwidth. The DSBTs ( ) can be allocated based on modulation format, center frequency, or both. The channelizer ( ) is therefore able to process narrowband carrier data streams as well as wideband carrier data streams. One embodiment of the channelizer ( ) has a plurality of sub-channelizers ( ) and a switch matrix ( ). The sub-channelizers ( ) filter individual carrier data streams from a multi-carrier data stream. The switch matrix ( ) is coupled to the sub-channelizers ( ) and routes the individual data streams to the sub-channelizers ( ) in a desired configuration.

Channelizer for a multi-carrier receiver

Receiver including low noise amplifier and frequency down-converter for a wireless telecommunication system

Multi-carrier receiver for a wireless telecommunication system

An analog-to-digital converter ( ) that employs delta-sigma technology, and has particular use in a receiver for a wireless telecommunications system. The converter ( ) includes a delta-sigma modulator ( ), having a summing junction ( ) that receives the analog input signal to be converted. A feedback from the output of a comparator ( ) is subtracted from the analog input signal to generate a difference signal that is then filtered, amplified and applied to the comparator ( ) for digital conversion. A sample and hold circuit ( ) receives the difference signal and holds the signal for a predetermined period of time so that the input to the comparator ( ) is stable. A differential limiting amplifier ( ) is employed to make the high data rate output of the comparator ( ) stable. The differential limiting amplifier ( ) can be within the comparator ( ) itself, or in the feedback path. In one embodiment, the differential amplifier ( ) employs a Schottky diode clamp ( ).

Continuous time delta-sigma modulator

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Manhattan Beach, CA, United States of America

William Marvin Skones