International Business Machines Corporation

Hewlett-packard Company

William M Zevin

Daniel Mark Dreps

Gordon Taylor Davis

Kevin Charles Gower

Kyu-hyoun Kim

Baiju Dhirajlal Mandalia

Robert Brett Tremaine

Michael Anthony Sorna

John C Sinibaldi

Michael Kevin Kerr

James A Mossman

David William Mann

Lydia Mai Do

Judith Marie Linger

Robert D Gronlund

Karl-Heinz Ziegenhain

Brian A Willette

A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

Strobe offset in bidirectional memory strobe configurations

Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.

Column address strobe write latency (CWL) calibration in a memory system

Methods and associated apparatus for analyzing and presenting captured state logic data including memory accesses by an intelligent I/O interface device and an attached computer system. The data analysis and display of the present invention aids an engineer in locating data corruption failures in a system. The heuristic analysis of the methods of the present invention locate and identify buffers accessed within the captured state logic data and buffer descriptors accessed within the captured state logic data despite the time dispersion thereof. The buffers and buffer descriptors located and identified within the captured state logic data are displayed on a computer display screen in a manner to more effectively assist an engineer in locating a root cause of data corruption than was possible with prior methods devoid of the analysis of the present invention. In particular, the display visually identifies buffers regardless of the state/time dispersion in the original captured state logic data and distinguishes read access from write access thereto. The display includes indicia used to associate a located and identified buffer descriptor with the identified buffer to which it refers. In response to user requests, the data contained in a selected buffer or selected buffers may be textually displayed either in a raw form or in accordance with the protocol specifications of the underlying data exchange application being debugged. The identified buffers may also be easily searched for a user specified string without concern for the time dispersion of the buffers in the captured state logic data.

Method and apparatus for correlating logic analyzer state capture data

A method and system in a data communications system for automatically determining a data communication device type and a transmission speed associated with the data communication device type. An incoming communication is detected on a transmission line, and transmit and receive hardware are connected to the transmission line. Next, a sequence of different signals in either a first communication protocol or a second communication protocol are transmitted from a first data communication device via a transmission line. The transmission line is then monitored for a response signal from a second data communication device. The response signal is initiated from the second data communication device in response to receipt of a particular signal within the transmitted sequence of different signals. Utilizing the relationship between the response signal and the transmitted sequence of different signals, a data communication device type and transmission speed are determined, and data communications may then be established between the first data communication device and the second data communication device at an optimal transmission speed.

Method and system for automatically determining data communication

An apparatus for efficient computation of a demodulation process on a digital signal processor for a sampled signal, which includes programming a digital signal processor to apply the sampled signal to an interpolating filter to add interpolation samples to the sampled signal, to search the sampled signal for a threshold crossing associated with a start bit, performing a linear interpolation to find a point where the threshold crossing occurs when a threshold crossing is detected, responsive to determining the point of the threshold crossing, determining a center of a start bit when the point of the threshold crossing has been determined, calculating a supplemental delay, and determining center points for subsequent of data bits utilizing the supplemental delay period from the center of the start bit.

Method and system for interpolating baud rate timing recovery for

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Raleigh, NC, United States of America

William M Zevin