Motorola Corporation

Other

Freescale Semiconductor,inc.

William M Williams

Barbara Vasquez

Gregory L Westbrook

Scott E Lindsey

Patrick F Thompson

Richard Eguchi

Chu-Chung Lee

Peter R Harper

John W Stafford

Tu-Anh N Tran

Treliant Fang

Lih-Tyng Hwang

Lois E Yong

Marlene J Begay

Anthony Angelo

Patrick Thompson

Dieter Frentz

A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.

Integrated circuit with test pad structure and method of testing

A semiconductor wafer contact system includes a sealed bladder (32) containing incompressible material. The sealed bladder (32) presses against a flexible circuit layer (28) including an array of electrical contacts (30). The bladder (32) forces the array of electrical contacts (30) against a corresponding array of device electrical contacts (12) on die (11) of a semiconductor wafer (10). The bladder (32) adapts in shape to compensate for die level and wafer level irregularities in contact height and non-parallelism. Additionally, bladder (32) ensures a constant force between membrane contacts (30) and die contacts (12), across the entire wafer (10).

Semiconductor wafer contact system and method for contacting a

A process for using removable Z-axis anisotropically conductive adhesive material (21) which includes water, a matrix resin (23), and conductive spheres (22). The material (21) is suitable for providing temporary contact between electronic devices. In one embodiment, the material (21) is used to temporarily bond a semiconductor wafer (11) to a probe substrate (12) for wafer-level burn-in.

Process for electrically connecting electrical devices using a

A semiconductor wafer contact system includes a base substrate (13) which has an array of raised supports (18). The array of raised supports (18) are distributed in a pattern corresponding to the pattern of electrical contacts (12) on the semiconductor wafer (10), to be contacted. In between the base substrate (13) and the wafer to be contacted (10) is a flexible circuit layer (14) including an array of electrical contacts (15) having the same pattern as the contacts (12) of the wafer and the raised supports (18). The raised supports (18) provide focused and localized force, pressing the membrane test contacts (15) against the wafer electrical contacts (12).

A board (10) for testing an integrated circuit disposed on a semiconductor wafer. The board contains a plurality of substantially parallel signal layers (14) and power planes (16) that are supported and electrically isolated by a dielectric material (12). One or more constraint layers (18,20) are disposed in the dielectric material, and the constraint layers have a coefficient of thermal expansion of about 1-6 ppm/.degree.C. In a preferred embodiment, the dielectric material is a fluoropolymer with-a ceramic or silica filler, and the constraint layers are an iron-nickel alloy of about 30-40 percent nickel by weight. The board has thermal expansion characteristics substantially similar to silicon to ensure good contact to a silicon wafer during burn-in testing.

Integrated circuit testing board having constrained thermal expansion

A system and method for aligning a semiconductor device (10) to a fixture (11) is provided. A first physical alignment feature (12) on the semiconductor device (10) and a second physical alignment (24) on the fixture (11) mate to align and hold the semiconductor device (10) in place. In one embodiment the physical alignment features (12) and (24) are produced using standard photolithography techniques, resulting in precise alignment features. In another embodiment the physical alignment features (12) and (24) are designed and placed to control the direction the thermal expansion of the semiconductor device (10) relative to the fixture (11).

Method for aligning a semiconductor device

An integrated circuit test system provides a quick change flexible circuit membrane (214). The flexible circuit membrane is a quadrant based design which allows steep launch angles away from a rectangular die under test (112). The flexible circuit membrane is edge guided (308,309) for positioning and concentric alignment in a probe tooling fixture (212). The system may include a focusing force member (528) focusing force only at the test point locations in line with the die pad contact positions (512) which allows greater force to be concentrated on the contact area, and helps to alleviate the debris tracking or 'dust mop' effect. Additionally, a relieved area (620) may be provided on the pressure applicator (616) to prevent membrane droop or the pillowing effects.

Integrated circuit test system

A method for controlling a characteristic impedance during testing of a semiconductor die (13). The semiconductor die (13) is mounted in a TAB package (10 or 54 ) wherein the TAB package ( 10 or 54 ) lacks a ground plane. A conductive plate (40 or 70) is removably mounted to a test contact fixture ( 29 or 60 ) . The conductive plate (40 or 70) may be coated with a layer of dielectric material (50, 56, or 74) having a specified thickness. The layer of dielectric material (50, 56, or 74) contacts a plurality of conductive fingers (16). A microstrip transmission line is formed which includes the plurality of conductive fingers (16) , the layer of dielectric material (50, 56, or 74), and the conductive plate (40 or 70). The semiconductor die (13) is tested by a computer controlled automatic tester (28).

Method for electrically testing a semiconductor die using a test

A test contact fixture which uses a flexible printed circuit tape to make contact to the integrated circuit and to a rigid printed circuit board which is part of the test equipment. The flexible printed circuit tape is held tightly against a hardened steel support allowing extremely accurate alignment both horizontally and vertically. The mounting plate provides a ground plane so that each lead may easily be configured as a 50 ohm transmission line. Leads of the integrated circuit under test are held in contact with the conductive lines on top of the flexible printed circuit tape by externally applied pressure allowing extremely rapid loading and unloading of the fixture. The body of the integrated circuit is held clear of the contact surfaces allowing heat control fixtures to be used to control the temperature of the integrated circuit during testing.

Test contact fixture using flexible circuit tape

An engine tilting device for use in installing and removing engines from vehicles has a base plate provided with a plurality of apertures formed in a predetermined pattern to match bolt hole patterns of a variety of standard intake manifolds. The base plate is secured on an engine intake manifold after removal of the carburetor. In a first embodiment of the invention, a lifting tab is mounted by a lead screw mechanism for reciprocal linear movement with respect to the base plate. In a second embodiment of the invention, the lifting tab is mounted for independent reciprocal linear movement in two perpendicular directions by independent lead screw mechanisms. The lifting tab may be oriented as required to allow tilting of the engine during installation and removal.

Growing community of inventors

Gilbert, AZ, United States of America

William M Williams