Motorola Corporation

Freescale Semiconductor,inc.

William M Strom

Alexander James Elliott

William J Miller

L Mali Mahalingam

Lauriann T Carney

Kenneth C Ramsey

Timothy Lee Olson

Gary Carl Johnson

Frank J Mosna, Jr

A system of mold locks () is formed on a heatsink () of a packaged semiconductor to prevent/mitigate delamination. The mold locks () anchor a plastic mold compound () that forms the protective cover for the packaged semiconductor die. The mold locks () are miniaturized to allow the positioning of them within the flag portion of the heatsink () and leadframe () such that a semiconductor die can be anchored above the mold locks () formed within the flag portion of the heatsink/lead frame (). The miniaturized size of the said moldlocks (do not detract from the purpose of the die attach solder ().

Heatsink moldlocks

Miniature moldlocks for heatsink or flag for an overmolded plastic package

method for making a mount for at least two electronic devices forming a first mounting surface () from a material (), and forming a second mounting surface () from the material (). The first mounting surface () is connected to, but spaced from, the second mounting surface () by a mounting surface distance (). The method further comprises reducing the mounting surface distance ().

Method of making a mount for electronic devices

A semiconductor die (32) is disposed on a heat sink (22) in an electronic package (10). During assembly, a leadframe (20) is connected to the heat sink (22) by down-set tabs (14, 28), which are offset from the heat sink (22) and disposed within the boundary (19) in which the final package (10) will be molded. Individual heat sinks (22) are pre-out prior to molding the final packages (10). In one roach, pins (36) are used to connect down-set tabs (14, 28) to heat sink (22).

Leadframe assembly for conducting thermal energy from a semiconductor

A method for interconnecting electrical system components. A leadframe (10) having leads (11) is encapsulated within a molding compound to form a first section (36) of the interconnect package (35). The first section (36) optionally includes channels (54). A leadframe (20) having leads (22, 23) is encapsulated within a molding compound to form a second section (37) of the interconnect package (35). The first and second sections (36 and 37, respectively) are coupled together with an adhesive material (43). An end (44) is removed from the interconnect package (35) forming an edge (50). A bare semiconductor chip (51) is coupled to the edge (50).

Process for manufacturing a package for mating with a bare semiconductor

A lead frame package for housing an integrated circuit. A lead frame (11) having a plurality of leads (13) extending from at least three sides of the package. Lead frame (11) is formed having a first region (18), a transition region (19), and a second region (21). A distance between a heat sink (12) and the lead frame (11) may vary. The offset is chosen to compensate for a predetermined distance between the heat sink (12) and the lead frame (11) such that the lead frame (11) aligns to lead frame handling equipment. A single lead frame manufacturing setup can then be used. A slot (22) is formed in the lead frame (11) extending through the second region (21) and the transition region (19) into first area (18) providing a path for injecting an encapsulation material into a mold.

Lead frame assembly for surface mount integrated circuit power package

An interconnect package (35) for interconnecting electrical system components. A first leadframe (10) having leads (11) is encapsulated within a molding compound forming a first section (36) of the interconnect package (35). The first section (36) optionally includes channels (54). A second leadframe (20) having leads (22, 23) is encapsulated within a molding compound forming a second section (37) of the interconnect package (35). The first and second sections (36 and 37, respectively) are coupled together with an adhesive material (43). An end (44) is removed from the interconnect package (35) forming an edge (50). A semiconductor chip (51) is coupled to the edge (50).

Growing community of inventors

Chandler, AZ, United States of America

William M Strom