Motorola Corporation

Other

William M Peterson

Robert H Leivian

Sidney C Garrison

Karen E Jachimowicz

Davis H Hartman

Fred V Richard

Robert Michael Gardner

Diana C Chen

Barbara M Foley

Earnest J Johnson

Eugene Youjun Chen

Daniel S Marshall

Howard C Anderson

Mark S Frank

Patrick J O'Malley

Glenn A Glass

Christopher N Hume

A table-based wired information system includes a table having a plurality of actual positions designed to receive people and a monitor positioned so as to be observed by people at any of the plurality of actual positions. A flat ribbon cable with a plurality of electrical conductors less than the number of available positions is affixed to an under-surface of the table in a flat orientation by an adhesive backing. A plurality of vote boxes, each including a multi-position switch, are adhesively attached to the under-surface at each of the actual positions. The cable is coupled to the monitor system and each of the vote boxes is coupled to the cable intermediate the ends by a press-on insulation displacement connector.

Conference-table-based wired information system

A teleconference system including a plurality of personal presence cells positioned at a local communication site and at a remote communication site. The plurality of personal presence cells are characterized as either sensor cells or display cells. The sensor cells include at least one video camera positioned to sense and transmit an image of the local participant, and an image screen positioned to reflect an image of the local participant toward the at least one video camera and for viewing of an image through the screen. The display cells each include at least one projection display positioned to display a multi-dimensional image of a remote participant on a display screen. A transmission link interfaces the plurality of personal presence cells positioned at the local communication site and the plurality of presence cells positioned at the remote communication site.

Teleconference system with personal presence cells

Quantum random address memory apparatus including a low dimensional plurality of address ports, a plurality of nano-memory elements, nano-diodes coupling the address ports to a high dimensional plurality of the plurality of nano-memory elements, and data output ports and structure coupled to the plurality of nano-memory elements. The high dimensional plurality of nano-memory elements is greater than the low dimensional plurality of address ports by a number resulting in substantially error free memory recalls.

Quantum random address memory with nano-diode mixer

Quantum random address memory apparatus including a low dimensional plurality of address ports, a plurality of nano-memory elements, mixer elements coupling the address ports to a high dimensional plurality of the plurality of nano-memory elements, and data output ports and structure coupled to the plurality of nano-memory elements. The high dimensional plurality of nano-memory elements is greater than the low dimensional plurality of address ports by a number resulting in substantially error free memory recalls.

Quantum random address memory

Quantum random address memory apparatus including a low dimensional plurality of address ports, a plurality of magnetic nano-memory elements, mixer elements coupling the address ports to a high dimensional plurality of the plurality of magnetic nano-memory elements, and data output ports and structure coupled to the plurality of magnetic nano-memory elements. The high dimensional plurality of magnetic nano-memory elements is greater than the low dimensional plurality of address ports by a number resulting in substantially error free memory recalls.

Quantum random address memory with magnetic readout and/or nano-memory

A quantum random address memory with piezo readout includes a plurality of address ports providing a low dimensional plurality of addresses, readout structure including a piezo layer with a pair of readout terminals attached thereto, a plurality of nano-memory elements, a plurality of mixer elements coupling either the plurality of address ports or the piezo layer to a high dimensional plurality of the plurality of nano-memory elements, and the other of the plurality of address ports or the piezo layer being coupled to the plurality of nano-memory elements, wherein the high dimensional plurality of nano-memory elements is greater than the low dimensional plurality of addresses.

Quantum random address memory with piezo readout

Quantum pseudo-random address memory apparatus including a low dimensional plurality of address ports, a plurality of polymer nano-memory elements, polymer mixer elements coupling the address ports to a high dimensional plurality of the plurality of polymer nano-memory elements, and data output ports and structure coupled to the plurality of polymer nano-memory elements. The high dimensional plurality of polymer nano-memory elements is greater than the low dimensional plurality of address ports by a number resulting in substantially error free memory recalls.

Quantum random address memory with polymer mixer and/or memory

A neural network (10) organizes the data items into a graphically oriented format by retrieving data items from a database (68) where each data item has a plurality of attributes. The neural network is organized (102) such that data items having similar attributes are assigned to neurons located closer together. The neurons of the neural network are matched (104) with the data items from the database and stored in a cross reference table. The cross reference table is displayed (106) on a computer screen (108) in a graphical format so that user visually relates the food items and sees the similarities and differences in their attribute data by the proximity of the data items to one another. The graphic format allows easy visual interpretation of the data items. For large databases, multiple neural networks (110, 112) can be organized hierarchically.

Method of organizing data into a graphically oriented format

An artificial neural network performs error correction on an input signal vector. The input signal vector is process in a forward direction through synapses in each of a plurality of neurons for providing an output signal from each of the neurons. The output signals from the neurons are monitored until the one having the greatest activity level is identified. A reverse flow signal having a predetermined magnitude is processed in the reverse direction through the neuron having the greatest activity level for updating the input signal vector. Alternately, the output signals of competing neurons may be applied through synapses weighted to favor the neuron having the greatest output signal activity. Thus, the neuron with synapses most closely matched to the elements of the input signal vector overpowers the remaining neurons and wins the competition. Once the winning neuron is identified, its output signal is reverse processed through the respective neuron for providing an improved input signal vector with reduced noise and error. The improved signal is reprocessed in the forward direction through the neural network for providing higher confidence output signals.

Circuit and method of error correcting with an artificial neural network

A processing element utilizing the learning algorithm

Adaptive weight adjusting circuit for an neural network

An artificial neural network is provided using a digital architecture having feedforward and feedback processors interconnected with a digital computation ring or data bus to handle complex neural feedback arrangements. The feedforward processor receives a sequence of digital input signals and multiplies each by a weight in a predetermined manner and stores the results in an accumulator. The accumulated values may be shifted around the computation ring and read from a tap point thereof, or reprocessed through the feedback processor with predetermined scaling factors and combined with the feedforward outcomes for providing various types neural network feedback computations. Alternately, the feedforward outcomes may be placed sequentially on a data bus for feedback processing through the network. The digital architecture includes a predetermined number of data input terminals for the digital input signal irrespective of the number of synapses per neuron and the number of neurons per neural network, and allows the synapses to share a common multiplier and thereby reduce the physical area of the neural network. A learning circuit may be utilized in the feedforward processor for real-time updating the weights thereof to reflect changes in the environment.

Digital processing element in an artificial neural network

An artificial neuron is provided using a simple distance calculation between the input signal vector and the synapse weight signals for providing an output signal. A difference signal is developed by subtracting a weight signal from an input signal. The difference signal is processed through a weighting function having a predetermined polarity and accumulated for providing the output signal of the neuron. A digital embodiment is supported with a memory circuit for storing the digital weights and a memory lookup table or possibly a multiplexer circuit for weighting of the difference signal. An analog embodiment uses a plurality of comparators responsive to the input signal vector and the weight signals for providing the output signal of the neuron as the absolute value of the difference of the input signal vectors and the weight signals.

Simple distance neuron

An artificial neural network is provided using a modular, self-organizing approach wherein a separate neural field is contained within each module for recognition and synthesis of particular characteristics of respective input and output signals thereby allowing several of these modules to be interconnected to perform a variety of operations. The first output and second input of one module is respectively coupled to the first input and second output of a second module allowing each module to perform a bi-directional transformation of the information content of the first and second input signals for creating first and second output signals having different levels of information content with respect thereto. In the upward direction, the first low-level input signal of each module is systematically delayed to create a temporal spatial vector from which a lower frequency, high-level first output signal is provided symbolic of the incoming information content. Since the first output signal contains the same relevant information as the first input signal while operating at a lower frequency, the information content of the latter is said to be compressed into a first high-level output signal. In the downward direction, a second output signal having a low-level of information content is synthesized from a second input signal having a high-level of information content. The second input signal is the best prediction of the first output signal available from the knowledge base of the module, while similarly the second output signal is the prediction of the first input signal.

SPANN: Sequence processing artificial neural network

A neural network is provided for performing bi-directional signal transformations through a matrix of synapses by alternately sending and receiving signal vectors therethrough via switchable driver circuits. In the forward direction, the input signal is transformed according to the weighting elements of the synapses for providing an output signal. The drive direction of the switchable driver circuits may be reversed allowing the output signal to flow back through the same synapses thereby performing a reverse transformation, which may actually be an improved estimate of the original input signal. Sample and hold circuits are provided for latching the output signals of the switchable driver circuits back to the inputs thereof for repeated forward and reverse signal transformations until an acceptable transformation of the original input signal is realized, thereby achieving an improved estimate of the input signal and corresponding output transformation. More generally, a first input signal may be transformed in one direction through the synapses, while a second input signal, possibly independent and unrelated to the first input signal, may be reverse transformed in the opposite direction using the same synapses as the first direction.

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Chandler, AZ, United States of America

William M Peterson