Advanced Micro Devices Corporation

Samsung Electronics Co., Ltd.

William M Lowe

Hamilton B Carter

Leland Freddie Rusk

Christopher F Kiszely

According to one general aspect, an apparatus may include a trace control register, a first output path, and a second output path. The trace control register may be configured to receive one or more signals output by a combinatorial logic block. The trace control register may include a first register portion configured to capture the one or more signals. The trace control register may include a second register portion configured to capture whether an event occurred within the combinatorial logic block. The occurrence of the event is determined by at least a portion of the one or more signals having a predetermined state. The first output path configured to select between a plurality of captured signals provided by respective trace control registers. The second output path configured to output one or more captured events provided by one or more respective trace control registers.

Hardware profiling

A system and method for detecting timing-related functional problems in an HDL design of a computer system component are disclosed. A simulated model of the HDL design is supplied with a reference signal through a simulated bus. A bus transaction signal is then applied to the simulated model through the same or different simulated bus. The delay between the bus transaction signal and the reference signal is then varied over a range of values, and the simulated model's response to the bus transaction signal for each such delay value is received and analyzed by a transaction checker stored in the computer system memory. The duration of the bus transaction signal may also be varied. This methodology allows conversion of system waveform relationships, which could be observed on a physical system incorporating a manufactured version of the computer system component under test, into simulation waveforms with the same relative relationship. Problems that were once found only after the device was manufactured can now be detected prior to the manufacturing stage.

Transaction based windowing methodology for pre-silicon verification

A method and apparatus are presented for performing intrusive testing in order to verify proper operation of a microprocessor 'feature'. The method includes providing a microprocessor model which includes a representation of the feature to be tested. The feature operates in one of several different operating modes as determined by the states of one or more control signals. Intruder logic, configured to restrict operation of the feature to a single desired operating mode, is introduced into the microprocessor model. The microprocessor model executes a testing program which requires operation of the feature and produces a result. The result produced by the microprocessor model is compared to an expected result. Any difference between the result produced by the microprocessor model and the expected result may be due to an error in feature hardware or the portion of the feature control circuitry associated with the selected operating mode. The microprocessor model may be a software implementation (i.e., a set of instructions) or a hardware implementation (i.e., a logic device).

Method and apparatus for intrusive testing of a microprocessor feature

A methodology that provides detection of cache coherency errors in addition to detection of inefficient cache use by a cache master is disclosed. A model of the cache with storage for the address and data contained in each cache line and a flag indicating the state of the cache line (e.g., MESI state, or other cache coherency protocol state) is utilized. In addition, the cache model object also holds a dynamically allocated list (the cycle list) of bus cycles. This list is used to store pointers to non-cache bus cycles initiated in the multi-bus system. Cache bus cycles can update the state of the cache model object and can also instruct the cache model to perform coherency tests on pending non-cache bus cycles in the cycle list. When all protocol tests for a non-cache bus cycle have been successfully completed, no further coherency tests are performed on that bus cycle. Cache master verification is also achieved by polling the cache model to determine source of target resolution cycles for a bus cycle initiated by bus masters. Thus, cache coherency and cache controller operations are efficiently checked.

Cache coherency detection in a bus bridge verification system

In a computer system having a bus bridge connecting a plurality of system buses, a methodology for checking completion of a bus cycle in a bus bridge verification system is disclosed. The methodology verifies that the bus bridge is asserting proper signals for each bus protocol. As each bus cycle begins, a state machine object corresponding to that bus cycle is instantiated and each byte of said bus cycle state machine object is checked for resolution. A stimulator object may provide a bus stimulus to said bus cycle state machine object which may update its states in response thereto. Upon transitioning into its holding state, the bus cycle state machine object may verify that each byte of its transaction is accounted for and has been routed to the proper destination. The state machine object for a particular bus cycle may contain storage for that bus cycle's properties such as clock cycle number, cycle address, cycle type, cycle data and the status of byte enables. This methodology maintains a static bus cycle object that can determine if its transaction has been resolved. The cycle-based approach avoids instances of false failures arising from address remapping, byte merging or byte collapsing.

State machine based bus cycle completion checking in a bus bridge

A transaction checking system and method to verify bus bridges in multi-master bus systems are described. A state machine model is created for each bus in the system. An initiator cycle list and a target cycle list store corresponding bus cycle state machine objects and transition their states according to bus signals. The bus cycle state machines provide a mechanism of persistent storage for other verification tasks. A bus bridge model may store a copy of each configuration register for the bus bridge, thereby monitoring current state of the bus bridge. False failures due to data merging, data collapsing and address remapping are avoided. A cache model and a cycle-based messaging system provide verification of proper cache master operation. Cache coherency errors may also be detected. A statistics keeping object may be created to monitor and store all pertinent performance information for the bus bridge. The transaction checking system may monitor the state of the bus bridge in a device independent manner and with tighter verification. The cycle-based approach to verification of internal states of a bus bridge results in a sound resolution of bus cycles with a better predictability of possible failures.

Transaction checking system for verifying bus bridges in multi-master

A system and a method to monitor performance and resource utilization for a bus bridge in a computer system are described. All pertinent performance information for the bus bridge is stored in a statistics keeping or monitor object. A bus object is created for each bus in the system. Each bus cycle object receives the current cycle count and sends elapsed time information to the monitor object. A plurality of cycle list objects can also be used to track resource usage by sending messages to the monitor object indicating the type of cycles that enter the bus bridge. The monitor object then tracks the number of pending cycles that accumulate within the bus bridge. Thus, the statistics keeping object can indicate the current usage of each tracked resource.

State machine based bus bridge performance and resource usage monitoring

Presented are a method an apparatus for operational verification of a microprocessor subject to an interrupt during a 'target' activity. A software model of the microprocessor allows determination of the start and end of the target activity via one or more signals generated during the target activity. A testing program causes the microprocessor model to produce a timing signal (i.e., a trigger event) a number of system clock cycles (i.e., a delay time) before the target activity begins. A software memory model coupled to the microprocessor model includes an interrupt signal generator. The interrupt signal generator receives the trigger event and generates an interrupt signal after the delay time expires following the trigger event. A simulation trace obtained during a first 'characterization' procedure is used to determine the delay time. Following the characterization procedure, the microprocessor replaces the microprocessor model. Execution of the testing program by the microprocessor causes the interrupt to occur during the target activity, and causes the microprocessor to produce a test result. The test result is compared to an expected result to determine proper operation. The microprocessor model and the memory model are contained within a memory unit of a microprocessor testing system during testing. The microprocessor testing system includes a central processing unit (CPU), chip set logic, a system bus, and a memory bus in addition to the memory unit.

Method and apparatus for the operational verification of a

An internal clock generation circuit is provided for receiving an external clock signal. Based upon the duration of each high and low pulse width of the external clock signal, the internal clock generation circuit selects one of two possible clock signals as an internal clock signal for connection to a load device. Selection is based upon whether the high and low pulse durations of the external clock signal exceed or are less than a threshold amount. If exceeded, the external clock signal connects a longer duration pulse width internal clock signal to the load device. If less than, the internal clock signal connects a shorter duration internal clock signal to the load device. Accordingly, the internal clock generation circuit allows for variability in the external clock signal frequency and duty cycle and correspondingly selects one of two (and possibly more) clock signals for connection to the load device. Detection and selectability allows for load device operation at speeds less than maximum designed amounts in order to salvage slower speed devices and improve wafer yield.

Internal clock signal generation circuit having external clock detection

A clocking disable and enable circuit is provided having an input for receiving a clocking signal and another input for receiving a disable/enable signal. The disable and enable circuit provides a clocking disable/enable output from the circuit which is synchronized with the clocking signal during times in which the disable/enable signal is not activated. At times during which the disable/enable signal is activated, the clocking disable/enable signal transitions after at least a one half clocking period to a steady state value (either high or low voltage level). After the disable/enable signal becomes inactive again, clocking disable/enable signal automatically resynchronizes to the clocking signal. The clocking disable and enable circuit herein is well suited for providing glitch-free transition between a clocking state and a steady state to a synchronized digital or analog circuit which depends upon clocking synchronization for its operation. The clocking disable and enable circuit herein is also well suited for providing temporary halt to the connected digital or analog circuit as well as providing periods of selective demodulation associated with frequency tracking communication systems.

Synchronized clocking disable and enable circuit

There is disclosed an improved clock generator responsive to a first clock signal having a frequency f.sub.1 and a second clock signal having a frequency f.sub.2, wherein f.sub.2 is equal to nf.sub.1. The clock generator provides a fixed duty cycle clock signal having a period equal to n complete cycles of the second clock signal and being at a first level for m complete cycles of the second clock signal and a second level for n-m complete cycles of the second clock signal. The clock generator includes a counter for counting half-cycles of the second clock signal to derive the first and second levels, and a flip-flop for establishing a timing condition responsive to the first clock signal. The clock generator further includes an inhibit circuit coupled to the counter for enabling the counter to begin a new counting period in response to the counter counting n complete cycles of the second clock signal and the establishment of the timing condition. The clock generator inhibit circuit guarantees a consistent duty cycle signal output immune to variations of the period of the first clock signal to as low as n-1/2 complete cycles of the second clock signal.

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Austin, TX, United States of America

William M Lowe