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United States of America As Represented by the Secretary of the Air Force

William M Kaupinis

Michael A Davis

Stanley M Nissen

Peter F Barbella

Jeffrey E Carmella

Malcolm F Crawford

Chris J Grobicki

A method for calibrating the radar system includes the steps of: replacing stored statistically generated 'average' error correction coefficients with error correction coefficients personal to a missile under test. More particularly, stored in the missile's memory are: (a) first personalized error correction coefficients generated in response to test signals produced internal to the missile and injected into a monopulse arithmetic unit for the missile's receiver/processor; and (b) a second set of personalized error coefficients generated in response to test signals external to the missile and injected through the missile's antenna to the receiver/processor. The missile includes a radio frequency (R.F.) energy test signal generator for performing a test during the missile's flight to determine 'in-flight' personalized error correction coefficients. The test is performed in-flight by injecting the R.F. energy test signal generated internal to the missile during the missile's flight into the monopulse arithmetic unit for the receiver/processor. The receiver/processor: (a) compares the first set of error correction coefficients with the 'in-flight' error coefficients and adjusts the second set of error correction coefficients in accordance with such comparison; and, (b) if R.F. energy external to the missile is less than a predetermined threshold level, uses the adjusted second set of coefficients during the missile's flight to produce boresight error signals; otherwise, the receiver/processor uses unadjusted first set of error correction coefficients.

Guided missile calibration method

A multi-microprocessor apparatus utilizing a plurality of central processing units arranged in a parallel configuration. Each central processing unit which has its own local memory unit, communicates with a common memory unit on a time shared basis that is synchronized between each central processing unit and the common memory unit.

Plurality of processors where access to the common memory requires only

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Methuen, MA, United States of America

William M Kaupinis