Samsung Electronics Co., Ltd.

Nortel Networks Corporation

William M Hurley

Lup Meng Loh

John Alexander Interrante

Michael Brobston

Jordan Charles Mott

Yinong Ding

Yaming Zhang

Johnny T Homer

Weon-Ki Yoon

Warren T Pottenger

Avery Cox Topps

WeonKi Yoon

J Alexander Interrante

Yoonyoung Park

Daniel D Lewallen

John Alex Interrante

An apparatus and method reduce distortion in a processed signal. The apparatus includes a first receive path, a second receive path, a summation unit, and a compensation unit. The first receive path is configured to process a received analog signal into a first digital signal. The second receive path is configured to process the received analog signal with a phase shift into a second digital signal. The summation unit is configured to sum the first and second digital signals to form a processed digital signal. The compensation unit is configured to identify a conjugate of the processed digital signal, apply a weighting factor to the conjugate of the processed digital signal to form a weighted signal, and subtract the weighted signal from the processed digital signal to reduce the distortion.

Digital I/Q imbalance compensation in a quadrature receiver

An apparatus for envelope tracking calibration for use in a wireless communication is provided. The apparatus includes a transmission signal path configured to carry a transmission signal to an antenna. An envelope signal path configured to feed an envelope signal with an envelope tracking power amplifier. A controller is configured to transmit a normal envelope signal being generated in a normal operation mode and measure a first Adjacent Channel Leakage Ratio (ACLR) corresponding to the normal envelope signal. The controller is further configured to transmit a comparison envelope signal being generated in a comparison operation mode and measure a second ACLR corresponding to the comparison envelope signal. The controller is configured to calculate a time misalignment between the transmission signal path and the envelope signal path based on a difference between the first and second ACLRs.

Apparatus and method for enveloping tracking calibration

A method for partitioning gain for a wireless radio frequency integrated circuit (RFIC) is provided. The method includes receiving an overall gain at the RFIC from a baseband controller that is coupled to the RFIC. The overall gain is then partitioned in the RFIC.

Method and system for partitioning gain for wireless radio frequency integrated circuits

A system and method for minimizing a DC component of a received signal are disclosed. As one example, a system for minimizing a DC component of a signal in a wireless receiver is disclosed, which includes a programmable filter operable to filter the signal with at least one of a low cutoff frequency and a high cutoff frequency, and a transition unit coupled to the programmable filter, the transition unit operable to transition the programmable filter between the high cutoff frequency and the low cutoff frequency.

System and method for DC correction in wireless receivers

A reconfigurable RF transceiver for use in either a base station or a mobile station Of a wireless network. The reconfigurable RF transceiver comprises a first receive path that down-converts an incoming RF signal to analog and digital baseband signals. The first receive path in a first mode down-converts the incoming RF signal in a receive frequency band for the base station and in a second mode down-converts the incoming RF signal in a receive frequency band for the mobile station. The reconfigurable RF transceiver further comprises a transmit path for up-converting an outgoing baseband signal to an outgoing RF signal. The transmit path in the first mode up-converts the outgoing baseband signal in a transmit frequency band for the base station and in the second mode up-converts the outgoing baseband signal in a transmit frequency band for the mobile station.

Reconfigurable base station using mobile station RF ASIC

Apparatus and method for regulating data in a signal processing pipeline are disclosed. For example, an apparatus is disclosed that includes a first element operable to determine a time interval between a first plurality of data samples input to the signal processing pipeline, and calculate a sample spacing count value associated with the time interval, a second element coupled to the first element, the second element operable to hold the sample spacing count value until the time interval between the first plurality of data samples is changed, a third element coupled to the second element and the signal processing pipeline, the third element operable to output a control signal to the signal processing pipeline, and responsive to the control signal, the signal processing pipeline operable to output a second plurality of data samples.

Apparatus and method for regulating bursty data in a signal processing pipeline

An apparatus and method for flexible visibility in an integrated circuit are disclosed. As one example, an apparatus for flexible visibility in an integrated circuit is disclosed. The apparatus includes a switch unit disposed in the integrated circuit, the switch unit configured to receive a plurality of signals associated with a plurality of visibility points in the integrated circuit, and output the received plurality of signals in a serial form. Also, the apparatus includes a formatter unit disposed in the integrated circuit and coupled to the switch unit, the formatter unit configured to receive the plurality of signals in the serial form, and output a plurality of formatted signals including the received plurality of signals.

Apparatus and method for flexible visibility in integrated circuits with minimal package impact

A Coordinate Rotation Digital Computer (CORDIC) circuit capable of performing precise vector rotation, including a pre-rotation stage configured to selectively rotate an input vector by &#xb1;90 degrees and to produce a pre-rotated vector. A first stage is configured to perform a first set of iterative CORDIC calculations on the pre-rotated vector and to produce a first rotated vector and a remaining rotation value. A second stage configured to perform a second set of iterative CORDIC calculations on the first rotated vector and to produce a second rotated vector, the second rotated vector corresponding to the input vector.

Apparatus and method for optimal implementation of the CORDIC algorithm for wireless RFIC digital down-conversion

The present disclosure relates generally to systems and methods for tuning power consumption and group delay in circuits such as radio frequency integrated circuits (RFICs). In one example, a system includes first and second gating blocks configured to reduce a first clock signal operating at a first clock rate to a second clock rate and a third clock rate, respectively. A first processing block coupled to the first gating block operates at the second clock rate. A second processing block is coupled to the first processing block and the second gating block, and operates at the third clock rate. The first processing block changes a flag state from a first state to a second state when transmitting a first data sample to the second processing block, and changes the flag state from the second state to the first state when transmitting a second data sample to the second processing block.

System and method for tuning power consumption and group delay in wireless RFICs

A system and method for configuring a wireless transceiver are disclosed. As one example, a system for configuring a wireless transceiver is disclosed, which includes a first data storage unit coupled to a configuration bus disposed in the wireless transceiver, a second data storage unit coupled to the configuration bus, a change detection unit coupled to the second data storage unit, the change detection configured to detect a change to a value stored in the second data storage unit, and output a signal responsive to the change, and a third data storage unit coupled to the first data storage unit, the second data storage unit, and the change detection unit. The third data storage unit is configured to store a plurality of predefined configuration data sets, and convey a predefined configuration data set to the first data storage unit responsive to the signal.

System and method for rapidly configuring wireless transceivers

A method for providing access arbitration for an integrated circuit in a wireless device is provided. The method includes receiving a command from a processing element coupled to the integrated circuit. A preempt signal associated with the command is generated. The preempt signal is operable to identify a priority for the command as one of high and low. The preempt signal is provided to an access arbiter for use in providing access arbitration for the command.

Method and system for providing access arbitration for an integrated circuit in a wireless device

A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal processing chain, and a checksum calculator coupled to an output of the digital signal processing chain.

System and method for self-test of integrated circuits

A method for converting logarithmic values into linear values in digital logic is provided. The method includes receiving a logarithmic gain signal. A shift signal is generated based on the logarithmic gain signal. A remainder signal is generated based on the logarithmic gain signal. A linear gain is applied to a digital input signal based on the shift signal and the remainder signal to generate a digital output signal.

Method and system for converting logarithmic values into linear values in digital logic

A method for providing analog control of digital gain in a wireless device is provided. The method includes receiving an analog gain from a baseband modem at a radio frequency integrated circuit (RFIC) having a digital region. The baseband modem is associated with a first operating range, and the digital region of the RFIC is associated with a second operating range. The analog gain is compatible with the first operating range. A digital gain is generated based on the analog gain. The digital gain is converted into a modified digital gain compatible with the second operating range.

Method and system for providing analog control of digital gain in a wireless device

A circuit and method for providing a power-on self test capability for peripheral devices that allows direct testing of address-line data. The preferred embodiment includes a multiplexer circuit that allows the read address line outputs of a microprocessor to be directly returned to the data inputs of the microprocessor, thus providing a direct verification of the integrity of the read-address connection.

Growing community of inventors

Wylie, TX, United States of America

William M Hurley