International Business Machines Corporation

William M Chu

Edward B Eichelberger

David V Horak

Wesley Charles Natzle

Todd Christopher Bailey

Chienfan Yu

Sadanand Vinayak Deshpande

Richard Frank Rizzolo

Scott W Crowder

Francis H Chan

Hung Y Ng

Len Yuan Tsou

William A Muth

Stephen E Bello

George Sonoda

David A Kiesling

James M Lee

Frederick William Buehrer

John A Ludwig

Andrew Z Muszynski

Derek Chen

Carl K-l Wong

Rolf O Bergenn

A method provides improved alignment for a photolithographic exposure. In such method, a first exposure tool and a first chuck used in a reference photolithographic exposure of a first material layer on a substrate can be identified. The substrate typically includes at least a semiconductor layer. The first chuck typically is one of a plurality of chucks usable with the first exposure tool. The method may further include identifying a second exposure tool and a second chuck used in a current photolithographic exposure of a second material layer on the substrate. In one embodiment, alignment correction information specific to each of the identified first exposure tool, the first chuck, the second exposure tool and the second chuck can be used in aligning the semiconductor substrate to a second exposure tool and a second chuck. In one embodiment, such method can compensate for alignment error caused by differences between the first and second exposure tools, between the first and second chucks, or between the first and second exposure tools and between the first and second chucks.

Alignment method for semiconductor processing

A blocking layer is formed on a hard mask having an initial thickness. Lines are fabricated by patterning the blocking layer and the hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the blocking layer and the substrate to form the line segment with a second dimension across the line segment that is smaller than the first dimension. The blocking layer prevents the formation of reaction product on the hard mask so that the initial thickness of the hard mask is maintained. The blocking layer can also serve as an ARC layer for photoresist patterning so that the use of an additional film layer is not required.

Vapor phase etch trim structure with top etch blocking layer

A three-level input voltage level conversion circuit for three-level emitter coupled logic (ECL) cascode circuit provides three unique input levels. The input voltage level conversion circuit has a level shift up circuit for the top level input, a direct input to the middle level input, and a conventional emitter follower input for the bottom level input. The shift up circuit consists of a differential pair with differential inputs to the bases of each transistor. The collectors of these transistors are coupled to the upper level of the three-level cascode logic circuit. The emitters of the differential pair are coupled to the collector of a current source transistor. The base of the current source transistor is connected to an activation potential, and the emitter is coupled through a resistor to a reference potential. The down shift is accomplished with a differential transistor pair with bases directly coupled to a differential input pair. The collectors of these transistors are coupled to a positive potential and the emitters are coupled through resistors to a reference potential. The emitters are the differential output of the circuit and are directly coupled to the lower level of the cascode circuit.

Three-level cascode differential current switch

A digital data transceiver comprises a conventional push-pull driver and a novel receiver. The transceiver can drive data to and simultaneously receive data from a transceiver of like kind via the same communication line. A series resistor is situated between the driver's output and the communication line. The resistor has equivalent resistance to the characteristic impedance of the line in order to prevent undesirable reflections on the line. In the receiver, the driver's output is divided in half by a resistor voltage divider for input to a differential current mechanism. The differential current mechanism has a differential current switch and a feedback circuit. The differential current switch compares the signal levels at both ends of the series resistor to derive an output for the receiver. The feedback circuit provides feedback to the differential current switch to increase the noise margin.

Simultaneous bidirectional transceiver

A low power push pull off chip driver for differential cascode current circuitry is described that includes the collectors of a differential pair directly coupled to bases of a push pull driver and level shifters coupled to the input of the differential pair to prevent saturation of the differential pair.

Low power push pull driver

A masterslice cell wireable to form any of a selected book set of two level differential cascode current switch basic circuits. Twenty percent increased performance is provided as compared with ECL masterslice circuits running at the same power. In spite of increased wire due to differential logic, and potential increased complexity in design software, the invention is actually readily adaptable to existing masterslice design systems.

Two-level differential cascode current switch masterslice

An FET load gate compensator employing feedback to control the load gate voltage holds the circuit delay and power dissipation of an integrated circuit nearly constant. The integrated circuit chip is provided with several stages of inverters which act as a delay sensor to simulate the delay of the operational circuit on the chip. The time delay of the delay sensor on the integrated circuit chip is compared with an external clock reference by a delay comparator. The delay comparator generates an output voltage which is used to adjust the load gate voltage until the delay in the delay sensor is equal to the clock reference. Since the same load gate voltage is distributed in the rest of the operational circuits in the integrated circuit chip, the delay times of these circuits will track with that of the delay sensor and thus also tend to be held constant.

FET load gate compensator

Disclosed is a technique for testing electronic storage arrays including bistable storage cells fabricated in accordance with integrated semiconductor technology. Also described is the testing of load devices in a flip flop storage cell which is connected to a pair of bit lines that are inaccessible for the direct application of test signals. Testing is performed by altering the time duration of signals applied to the memory cells under test.

Test technique for semiconductor memory array

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Hyde Park, NY, United States of America

William M Chu