United Semiconductor Corp.

United Microelectronics Corp.

William Lu

Tsung-Yuan Hung

Ching-Hsing Hsieh

Shu-Jen Chen

Chih-Ching Hsu

Chien-Chih Lin

Chi-Cheng Yang

Yung-Chieh Kuo

A method of manufacturing an interconnect. A first conductive layer is formed on the wafer. Portions of the first conductive layer are removed to form a wire in the interior region and to expose the surface of the wafer in the edge region, simultaneously. An insulating layer is formed on the wire and the wafer. An opening is formed to penetrate through the insulating layer and exposes the wire. A second conductive layer is formed on the insulating layer and fills the opening.

Method of manufacturing interconnect

A method for fabricating a shallow trench isolation (STI) structure includes a pad oxide layer and a hard masking layer are sequentially formed over a semiconductor substrate. A trench is formed in the substrate by patterning over the substrate. Then, the hard masking layer is removed to expose the pad oxide layer. An insulating layer is formed over the substrate to fill the trench. Using the pad oxide layer as a polishing stop, a CMP process is performed to polish the insulating layer until the pad oxide layer is exposed. The remained pad oxide within the trench is simultaneously planarized to have a planar top surface without dishing and microscratch. After the pad oxide is removed, the STI structure is accomplished.

Method for fabricating a shallow trench isolation structure

A method for fabricating a STI structure includes a pad oxide layer and a hard masking layer are sequentially formed over a semiconductor substrate. A trench is formed in the substrate by patterning over the substrate. A liner oxide layer is formed over a side-wall of the trench in the substrate. An isolating layer by APCVD and an isolating layer by HDPCVD are sequentially formed over the substrate, in which the height of the CVD isolating layer within the trench is lower than the height of the hard masking layer. A CMP process is performed, using the hard masking layer as a polishing stop. The hard masking layer and the pad oxide layer are removed to accomplish the STI structure.

Method for fabricating a shallow trench isolation

A method for fabricating a via that uses a hard etching mask for etching the via. A photoresist layer used to pattern the hard etching mask is removed before starting the via etching. The hard etching mask includes a TiN etching mask, a silicon nitride etching mask, and a oxide/TiN etching mask. For each different etching mass, the TiN etching mask is not necessarily removed after etching; the silicon nitride etching mask is removed after etching; the oxide layer in the oxide/TiN etching mask is sacrificial layer.

Method for fabricating a via

A method of forming a via is provided comprising a plasma treatment at the spin-on-glass layer after forming the unlanding via. The plasma comprises hydrogen and a second gas. The mist containing in the spin-on-glass layer is damaged and removed away.

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Tai-Ping, Taiwan

William Lu