Micron Technology Incorporated

Seiko Epson Corporation

William Low

Rajesh Sundaram

Sowmiya Jayachandran

George Lyons

David M Tucker

According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

Apparatuses and methods for exiting low power states in memory devices

According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

Multiple independent images are presented on multiple display devices by driving the display devices with a common set of control signals and a multiplexed set of data signals that convey information representing interleaved components of each independent image. In a preferred embodiment, a unique clock signal is provided to each respective display device that is aligned with the interleaved components of the image to be presented by that respective display. The control, data and clock signals may be obtained by multiplexing control and data signals received from display pipeline circuits, or by generating the, signals using a composite circuit that implements the features of two or more multiplexed display pipeline circuits.

Presenting independent images on multiple display devices from one set of control signals

A clocking system including a line clock system for generating normal line clock pulses to the digital display during the period when the image is being rendered and for generating fast line clock pulses to the digital display during the vertical blanking period to address the otherwise unaddressed vertical region. The clocking system further includes a pixel clock system for generating normal pixel clock pulses to the digital display during the period when the image is being rendered and for generating fast pixel clock pulses to the digital display during the horizontal and vertical blanking periods to address the otherwise unaddressed horizontal and vertical regions.

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Vancouver, Canada

William Low