Linear Technology Corporation

Analog Devices,inc.

Analog Devices International Unlimited Company

William Louis Walter

Vincenzo DiTommaso

Kenneth J Stern

Edward B Hilton

Thomas Alan Gaiser

Sauparna Das

Farhad Vazehgoo

A Paul Brokaw

Samuel Hodson Nork

Steven Leo Martin

Joseph Sinohin Panganiban

Charge pumps with accurate output current limiting are provided herein. In certain embodiments, a charge pump includes an output terminal for providing a regulated output voltage, a switched capacitor, and switches that control connectivity of the switched capacitor to selectively charge or discharge the switched capacitor. The switches are operable in two or more phases including a charging phase in which the switched capacitor is charged with a charging current and a discharging phase in which the switched capacitor is coupled to the output terminal. The charge pump further includes an output current limiting circuit that controls the charging current to limit an amount of output current delivered by the charge pump to the output terminal. The output current limiting circuit limits the output current based on comparing a reference signal to an integral of an observation current that changes in relation to the charging current.

Charge pumps with accurate output current limiting

Circuits and methods for bidirectional power conversion are provided that allow mobile and other devices to generate power suitable to support multiple modes of operation. The bidirectional power converters of the present invention may operate in both step up and step down configurations rather than having a single dedicated conversion function and use many of the same components thereby reducing converter size and complexity.

Bidirectional power converters

Circuits and methods for bidirectional power conversion are provided that allow mobile and other devices to generate power suitable to support multiple modes of operation. The bidirectional power converters of the present invention may operate in both step up and step down configurations rather than having a single dedicated conversion function and use many of the same components thereby reducing converter size and complexity. In some embodiments, the converter of the present invention may be used to provide a power component of a communications link, such as a USB link.

The slew rate of switching circuits, e.g. for DC to DC converters, is controlled without unduly sacrificing total switching time, by providing a weaker switching transistor in parallel with each stronger main switching transistor. Switching of the weaker transistor is controlled so as to have a slower slew rate in transitions between switch states than transitions of the main transistor. The main transistor switches at a fast rate for efficiency, but the slower transition by the weaker transistor provides a more gradual transition of the voltage at the desired switching node, so as to reduce EMI and/or input supply noise.

Dual FET output stage with controlled output DV/DT for reduced EMI and input supply noise

A method and circuit for driving the gate of a MOS transistor having a negative or low threshold voltage negative, in which the driving circuit is formed on a single chip. A negative voltage is generated from a positive voltage to drive the gate of the MOS transistor negative. The MOS transistor may be a native NMOS transistor, and the negative voltage is generated for increasing source-drain impedance of the native NMOS transistor. On the other hand, the MOS transistor may be a PMOS transistor, and the negative voltage is generated for reducing source-drain impedance of the PMOS transistor. The MOS transistor can be used as an open-drain switch or a source follower.

Method and circuit for driving a gate of a MOS transistor negative

A disclosed amplifier and buffer circuit, for example for a linear voltage regulator, comprises an input gain stage, an integrator and a unity-gain output stage. An output stage compensation scheme enables stable operation over a broad range of output capacitance. For low to moderate output capacitance, the design of the output stage effectively pushes the output pole to high frequencies while an internal pole provided by the integrator is dominant and rolls off the gain at lower frequencies. For high output capacitance, an input impedance of the buffer couples the internal pole and output pole, such that the output pole becomes dominant while the internal pole gets pushed to higher frequencies, maintaining stability. This input impedance connection may utilize the base-emitter resistance of a bipolar junction transistor connected to the internal node, or the connection may use an MOS transistor and a separate RC circuit.

Compensation technique providing stability over broad range of output capacitor values

A circuit and method for regulating a voltage by means of a switched capacitor circuit including multiple switches and capacitors. The circuit is operable in a plurality of modes that match the power transferred by the switched capacitors to the power drawn by a load. Advantageously, the circuit and method increase the efficiency of the regulator circuit over varying input voltage levels and output current levels. In addition, the circuit provides lower output ripple than conventional charge pumps.

High-efficiency, low noise, inductorless step-down DC/DC converter

A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through. the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Precision set-reset logic circuit and method

A charge pump DC/DC converter with reduced noise at the input voltage source is provided. The present invention includes buck and boost DC/DC converters with added circuitry coupled between the input voltage and the switches which maintains a substantially constant input current on both phases of the charge pump clock. The added circuitry reduces input current variations to provide reduced noise at the input voltage source. Feedback loop circuitry coupled between the output node and the added circuitry varies the current through the switches to control the output current of the DC/DC converter in order to maintain the output voltage at the regulated value. The added circuitry may comprise a variable resistor, current mirror, or current mirrors.

Charge pump DC/DC converters with reduced input noise

A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Precision set-reset logic circuit

Apparatus for detecting a tooth of a body. The tooth has an edge terminating in a notch. The tooth and notch are disposed along an edge of the body. The apparatus includes a pair of Hall effect cells disposed adjacent to, and laterally disposed along, the edge of the body. A magnet is positioned to provide a magnetic field through the edge of the body and Hall effect cells. The magnitude of field passing through the Hall effect cells is related to the relative position between the tooth and Hall effect cells. The Hall effect cells produce an output voltage related to magnitude of magnetic field passing through the cell. A differencing circuit is fed by the pair of Hall effect cell produced voltages for producing a difference signal having a peak when the edge of the tooth is positioned between the pair of Hall effect cells. A peak detector detects the peak produced by the difference signal. A threshold circuit is fed by the differencing signal for producing a gating signal when magnitude of the difference signal exceeds a threshold level. The gating signal enables peak detector produced pulse to pass to an output of the apparatus and inhibits such detected peak from passing to the output in the absence of such gating signal. A threshold level adjusting circuit is responsive to the difference signal for tracking maxima in the difference signal and establishing the threshold level of the threshold circuit in accordance with the tracked difference signal maxima.

Magnetic field change detection circuitry having threshold establishing

A circuit for use with a magnetic sensing device having at least first and second sensors has a summing amplifier for providing a difference signal and a peak detector for detecting peaks in the difference signal. The peaks determine a spatial offset of a transition in a sensed body.

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Lowell, MA, United States of America

William Louis Walter