Advanced Micro Devices Corporation

Hewlett-Packard Company

Xilinx, Inc.

Ati Technologies Ulc

Advanced Micro Device, Inc.

William Louie Walker

Paul J Moyer

Gabriel H Loh

Marius Evers

John Kalamatianos

William Evan Jones, Iii

Yasuko Eckert

Jagadish B Kotra

Jay E Fleischman

Eric Christopher Morton

Michael Warren Boyer

Michael T Clark

Richard Martin Born

Paul Edward Kitchin

Michael L Golden

Sriram Srinivasan

Scott Thomas Bingham

Philip Ng

Vydhyanathan Kalyanasundharam

David S Christie

Joseph Lee Greathouse

Douglas Benson Hunt

Patrick Knebel

Steven Kommrusch

Tarun Nakra

Bryan P Broussard

Paul C Miranda

Stephen R Undy

Pongstorn Maidee

Patrick J Shyvers

Mark Henry Oskin

Elizabeth Morrow Cooper

Marko Scrbak

Akhil Arunkumar

Dilip Kumar Jha

Weon Taek Na

Richard H Lee

Philip L Vitale

Mark R Storey

Gautam Tarasingh Hazari

Nicholas Dean Lance

Durgesh Kumar

Richard Carlson

Cache replacement policies are described. In accordance with the described techniques, a request for data is received and a cache replacement policy controls how a controller responds to the request. The cache replacement policy assigns each cacheline a priority value, which indicates whether the cacheline should be preserved relative to other cachelines, in response to the request being a cache miss that necessitates eviction of at least one cacheline. The cache replacement policy decrements priority values until at least one cacheline achieves a minimum priority value, at which point a cacheline is evicted. The cache replacement policy designates certain cachelines as protected, either via a separate protected indicator or via the cacheline's priority value, which causes unprotected cachelines to be selected for eviction while favoring preservation of protected cachelines in the cache.

Super-temporal cache replacement policy

A cache cleaner controller is described. In one or more examples, an apparatus includes a cache directory including status bits associated with cache locations within cache storage and a cache cleaner controller. The cache cleaner controller is configured to detect that a cache cleaner threshold has been reached. The cache cleaner threshold defines that a threshold number of the status bits indicate data maintained at the cache locations, respectively, has been changed. The cache cleaner controller is also configured to cause the data indicated as changed by the status bits to be copied from the cache locations within cache storage to the physical volatile memory.

Smart cache cleaner

The disclosed device includes a processor and an interconnect connecting the processor to a memory. The interconnect includes an interconnect agent that can forward memory requests from the processor to the memory and receive requested data returned by the memory. The requested data can include information for a next memory request such that the interconnect agent can send, to the memory, a speculative memory request using information for the next memory request that was received in response to the memory request. Various other methods, systems, and computer-readable media are also disclosed.

Remote acceleration for data dependent address calculation

An entry of a last level cache shadow tag array to track pending last level cache misses to private data in a previous level cache (e.g., an L2 cache), that also are misses to an exclusive last level cache (e.g., an L3 cache) and to the last level cache shadow tag array. Accordingly, last level cache miss status holding registers need not be expended to track cache misses to private data that are already being tracked by a previous level cache miss status holding register. Additionally or alternatively, up to a threshold number of last level cache pending misses to the same shared data from different processor cores are tracked in the last level cache shadow tag array, and any additional last level cache pending misses are tracked in a last level cache miss status holding register.

Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches

Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

Processor-guided execution of offloaded instructions using fixed function operations

In response to eviction of a first clean data block from an intermediate level of cache in a multi-cache hierarchy of a processing system, a cache controller accesses an address of the first clean data block. The controller initiates a fetch of the first clean data block from a system memory into a last-level cache using the accessed address.

Re-fetching data for L3 cache data evictions into a last-level cache

An integrated circuit (IC) device includes a ring transport having a plurality of nodes and a wire interconnect coupling the plurality of nodes in a ring. The wire interconnect including a wire to transmit clock wake signals around the ring transport in advance of data signaling representing a data packet. Each node is to switch from a clock gated state to a clocked state responsive to receiving a clock wake signal. The ring transport further includes a sleep controller coupled to a select node of the plurality of nodes. The sleep controller is to configure the select node into a clock suppression state for a specified duration responsive to identifying an idle condition on the ring transport via monitoring of the wire. While in the clock suppression state the node suppresses further transmission of any clock wake signals received at the select node.

Ring transport employing clock wake suppression

A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.

Retaining cache entries of a processor core during a powered-down state

A processing system includes an interconnect fabric coupleable to a local memory and at least one compute cluster coupled to the interconnect fabric. The compute cluster includes a processor core and a cache hierarchy. The cache hierarchy has a plurality of caches and a throttle controller configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher of a cache of the cache hierarchy.

Memory request throttling to constrain memory bandwidth utilization

A processing system rinses, from a cache, those cache lines that share the same memory page as a cache line identified for eviction. A cache controller of the processing system identifies a cache line as scheduled for eviction. In response, the cache controller, identifies additional 'dirty victim' cache lines (cache lines that have been modified at the cache and not yet written back to memory) that are associated with the same memory page, and writes each of the identified cache lines to the same memory page. By writing each of the dirty victim cache lines associated with the memory page to memory, the processing system reduces memory overhead and improves processing efficiency.

Rinsing cache lines from a common memory page to memory

An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory. When a requested address is determined to not be currently tracked by either the coherence directory or the Bloom filter, tracking of the address is initiated in the Bloom filter, but not in the coherence directory. Initiating tracking of the address in the Bloom filter includes setting hash bits in the Bloom filter so that subsequent requests for the address will 'hit' the Bloom filter. When a requested address is determined to be tracked by the coherence directory, the Bloom filter is not used to track the address.

Using a bloom filter to reduce the number of memory addressees tracked by a coherence directory

Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

Probe interrupt delivery

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Fort Collins, CO, United States of America

William Louie Walker