International Business Machines Corporation

William Lloyd McNeil

Guy L Guthrie

William John Starke

Thomas L Jeremiah

Jeffrey A Stuecheli

Piyush Chunilal Patel

Hugh Shen

David Carl Frank

James Johnson Allen, Jr

Ronald J Cooper

Douglas H Cox

Terri L Tomlinson

Herbert Rivera-Sanchez

A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, a determination is made whether the memory access request hits or misses in a directory of the lower level victim cache. In response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache. The lower level victim cache preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.

Victim cache replacement

A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.

Chaining multiple smaller store queue entries for more efficient store queue usage

A cache memory includes a cache array including a plurality of congruence classes each containing a plurality of cache lines, where each cache line belongs to one of multiple classes which include at least a first class and a second class. The cache memory also includes a cache directory of the cache array that indicates class membership. The cache memory further includes a cache controller that selects a victim cache line for eviction from a congruence class. If the congruence class contains a cache line belonging to the second class, the cache controller preferentially selects as the victim cache line a cache line of the congruence class belonging to the second class based upon access order. If the congruence class contains no cache line belonging to the second class, the cache controller selects as the victim cache line a cache line belonging to the first class based upon access order.

Victim cache line selection

An on-chip clock generation system used the Serial Interface in an on-chip JTAG facility to write bit patterns in a shift register. The bit patterns are applied to control inputs of a clock generation circuit whose clock outputs are varied in accordance with changes to the bit patterns. By using the same facility to provide JTAG and clock functions the output clocks provided by clock generation circuit on the chip can be varied without using additional pins or the output clocks themselves.

Functional clock generation controlled by JTAG extensions

Internal clock signals generated on a chip can be viewed externally by multiplexing the clock signals and functional output signals to pin that are used to view or access the functional output signals. JTAG facilities already provided on the chip are used to generate control signals that drive the multiplexers. By so doing no new input or output facilities are required to view the clock signals.

Functional clock observation controlled by JTAG extensions

Scaling of video is performed using area weighted averaging of input pixels to calculate coefficients to multiply with luminescence and crominence of input pixels. Such coefficients are produced for both the vertical and horizontal scaling directions of the input video stream. When scaling down or scaling up, scaling is first performed in the vertical direction to produce partially scaled pixels, which are then utilized for scaling in the horizontal direction. When scaling up, a pre-interpolation or pre-replication process is utilized to double the inputted pixel grid which doubled pixel grid is then utilized to scale down to the desired pixel grid size, which is greater than the originally inputted pixel grid size.

System and method for scaling video

A system and method for controlling a communications adapter interface such that supplemental data can be interleaved with data being transferred. The interleaving is performed in a manner such that the supplemental data is transparent to the data mover portion of the communications adapter. The supplemental data can be transferred in either read or write cycles that are interleaved at the beginning, in the middle, or at the end of data bursts or block data transfers. As a result of the interleaving, the slave interface bus is more fully utilized because arbitration and bus ownership changes do not create unused cycles. The interleaving is accomplished by temporarily halting an existing transfer of data and transferring the requested supplemental data while the data transfer is halted. After the supplemental data is transferred, the transfer of the balance of the data block is then allowed to continue. In other words, the present invention 'steals' a cycle from the data transferror and uses this cycle to transfer supplemental data.

Growing community of inventors

Apex, NC, United States of America

William Lloyd McNeil