Advanced Micro Devices Corporation

International Business Machines Corporation

William Lloyd Bircher

Manish Arora

Madhu Saravana Sibi Govindan

Srilatha Manne

Nuwan S Jayasena

Yasuko Eckert

Alexander J Branover

Indrani Paul

Michael J Schulte

Maurice B Steinman

Shiva R Dasari

Wingcheung Tam

Aniruddha Dasgupta

Dongyuan Zhan

Madhu S S Govindan

Brian E Waldecker

Mahdu S S Govindan

The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.

Setting power-state limits based on performance coupling and thermal coupling between entities in a computing device

A system includes a functional unit, at least one cache coupled to the functional unit, and a power management unit coupled to the functional unit and the at least one cache, the power management unit configured to trigger the functional unit to initiate prefetching of data to repopulate the at least one cache prior to a predicted exit of the functional unit from an idle mode to an active mode. The system further may include a prediction unit to predict the exit from the idle mode for the functional unit as occurring a predetermined duration from an entry into the idle mode. The prediction unit may determine the predetermined duration based on a history of idle mode durations indicative of durations of previous instances in which the functional unit was in the idle mode.

Early cache prefetching in preparation for exit from idle mode

A scheduler is presented that can adjust, responsive to a thermal condition at the processing device, a scheduling of process threads for compute units of the processing device so as to increase resource contentions between the process threads.

Thermally-aware process scheduling

Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

Power gating based on cache dirtiness

A system for saving the architectural state of a processor is described. The system performs a save state operation, which involves, for each sector in a set of sectors of the architectural state, determining whether the architectural state for the sector has already been saved to a memory, and saving the architectural state for the sector to the memory when the architectural state for the sector has not already been saved to the memory. Each sector in the set of sectors comprises a different and separate portion of the architectural state of the processor. The system determines whether the architectural state for a given sector has already been saved to the memory by checking a needs-rinsing flag for the given sector. The needs-rinsing flag for the given sector is asserted upon modifying the given sector and cleared following the save state operation.

Saving the architectural state of a computing device using sectors

Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).

Predicting power management state duration on a per-process basis and modifying cache size based on the predicted duration

The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Using a linear prediction to configure an idle state of an entity in a computing device

Methods, systems, and media are provided for power management. The power management includes, but is not limited to storing at a computer system a history of canceled entries into a low power state that interrupted a transition of the unit from an active mode to the low power state and disallowing transition of the unit into the low power state when a number of canceled entries indicated by the history of canceled entries exceeds a canceled entry threshold.

Performance aware idle power management

A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state.

Idle phase exit prediction

A processor includes a plurality of exclusive resources, a shared resource, and a controller configured to manage power state transitions of each of the plurality of exclusive resources and the shared resource. The controller receives a request from a resource to transition from a first power state to a lower power state and, in response to receiving the request, the controller controls power state transitions of the resource according to a first power control threshold when the resource is one of the plurality of exclusive resources and according to a second power control threshold that is greater than the first power control threshold when the resource is the shared resource.

Power controller, processor and method of power management

An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.

Dynamic performance control of processing nodes

Method and apparatus for demand-based control of processing node performance

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is disclosed for option ROM characterization by establishing an isolating execution environment for an expansion adapter of a computer, the adapter having an option ROM containing initialization code for the adapter, executing the initialization code for the expansion adapter in the isolating execution environment, identifying operating characteristics of the option ROM, including characteristics of the option ROM unavailable prior to execution of the initialization code in the isolating execution environment, and allocating virtual memory address space in a normal execution environment of the computer to the option ROM of the expansion adapter in dependence upon the identified operating characteristics of the option ROM.

Structure for option ROM characterization

Methods, apparatus, and computer program products are disclosed for option ROM characterization by establishing an isolating execution environment for an expansion adapter of a computer, the adapter having an option ROM containing initialization code for the adapter, executing the initialization code for the expansion adapter in the isolating execution environment, identifying operating characteristics of the option ROM, including characteristics of the option ROM unavailable prior to execution of the initialization code in the isolating execution environment, and allocating virtual memory address space in a normal execution environment of the computer to the option ROM of the expansion adapter in dependence upon the identified operating characteristics of the option ROM.

Growing community of inventors

Austin, TX, United States of America

William Lloyd Bircher