The Charles Stark Draper Laboratory, Inc.

Other

Massachusetts Institute of Technology

The United States of America

Seal Incorporated

William L Robbins

Phillip Marlowe

Raanan A Miller

John P O'Brien

Wendell Eugene Rhine

William D Goodhue

John S Haggerty

George B Kenney

Dennis D Rathman

R Allen Murphy

John James Boyle

Robert E Eller

Annamarie Lightfoot

Julia Sigalovsky

Jonathan Jay Bernstein

Mark Joseph Mescher

Robert G Gels

Frank E Mullen

Theodore H Krueger

Theodore H Krueger, Jr

Embodiments of systems, methods, and computer-readable media for auditing electronic freight bills are disclosed. For example, one embodiment of the present invention is a method including the steps of receiving a first data source comprising a first set of data; receiving a second data source comprising a second set of data; generating a record comprising at least a portion of the first data set and at least a portion of the second data set; and conducting an audit of the record. In another embodiment, a computer-readable media comprises code for carrying out such a method.

Method, system, and computer readable medium for electronic auditing

One illustrative method includes receiving a first data set associated with a shipping manifest from a first shipping entity. The method also includes receiving a second data set associated with a user preference. The method additionally includes generating a shipping matrix based on the first data set and the second data set. The method also includes receiving a third data set associated with an invoice and including a first shipping cost. The method additionally includes determining a particular row of the shipping matrix based on the third data set. The method also includes determining a second shipping cost based on data from the particular row of the shipping matrix. The method further includes determining if the first shipping cost is within a predefined tolerance range of the second shipping cost.

Systems and methods for electronically generating and analyzing shipping parameters

Electrodes are positioned substantially in contact with at least one surface of a solid to generate or absorb alkali metals when a voltage is applied between the electrodes.

Alkali-metal generator and absorber

Method and apparatus for high field asymmetric waveform ion mobility spectrometry in an electronic chip assembly, including an input section, an ion filter and detection section and a control section, in which ion filtering proceeds in a planar chamber under influence of high field asymmetric periodic signals, with detection integrated into the flow path, for producing accurate, real-time, data for identification of a broad range of chemical compounds.

Spectrometer chip assembly

Method and apparatus for high field asymmetric waveform ion mobility spectrometry in an electronic chip assembly,, including an input section, an ion filter and detection section and a control section, in which ion filtering proceeds in a planar chamber under influence of high field asymmetric periodic signals, with detection integrated into the flow path, for producing accurate, real-time, data for identification of a broad range of chemical compounds.

An integrated circuit (IC) header subassembly includes a spacer mounted to the header. The IC die assembly, consisting of an IC die or IC die carrier assembly, is mounted to spacer which is mounted to the header. The coefficient of thermal expansion of the spacer is selected to be between the coefficient of thermal expansion of the IC die assembly and the header minimize stresses due to thermal expansion and contraction. In addition, the spacer is substantially smaller in width and length and the IC die assembly and the header whereby the IC die assembly appears to be pedestal mounted. By minimizing the length of the contacting surfaces between the spacer and the IC die assembly, the risk of warping or cracking due to differences in thermal expansion can be reduced. This allows for much larger IC dies and pixel arrays to be used.

Integrated circuit header assembly

An integrated circuit (IC) die carrier assembly includes a thinned IC die mounted to a substrate or carrier. The IC die is mounted to the carrier via a thin layer of glass. The carrier facilitates fixturing and provides support during the lapping process used to thin the die. Ball bonding, wire bonding, thin film or thick film conductors can be used to interconnect the pads on the IC die to the pads on the carrier. The coefficients of the thermal expansion of the IC die and the carrier are closely matched to avoid damage to the IC die due to uneven expansion of the thinned IC die relative to the carrier. The IC die carrier assembly is better suited for ultrahigh vacuum and high temperature environments than conventional IC die carrier assemblies.

Method for attaching a die to a carrier utilizing an electrically nonconductive layer

Intergrated circuit die assembly

An electronic device package is provided, consisting of reaction bonded silicon nitride structural and dielectric components and conductor, resistor, and capacitor elements positioned with the package structural components. The package consists of a ceramic package base characterized by a dielectric constant less than 6, of reaction bonded silicon nitride, or a heat spreader material. An electrical conductor is positioned on, embedded in, or attached to the package base for making electrical contact to an electronic device supported on the base and in preferred embodiments, a resistor is attached to the package base. The invention also provides package sidewalls connected to the package base, preferably of reaction bonded silicon nitride, and at least one electrical conductor extending to an outside surface of the package sidewalls for making electrical contact to an electronic device supported by the package base. The reaction formed electronic device packages of the invention provide the ability to support high device signal frequencies, high device operational temperatures, and high environmental temperatures, due to the characteristics of the package materials. The reaction formed electronic device packages of the invention may be produced with a nitriding process during which the overall package structure exhibits minimal shrinkage. As a result, the reaction formed electronic device packages of the invention may be shaped to finished dimensions before the nitriding process with complicated and tight-tolerance geometries of package structural, conducting, resistive, and capacitive components.

Net-shape ceramic processing for electronic devices and packages

A method of producing electronic device packages is provided, consisting of the steps of shaping a package preform and heating the package preform in a nitrogen-containing atmoshpere to nitride the package preform. The shaped package preform may consist of package base, sidewall, conductor, resistor, or capacitor components. The package base and sidewall components may be formed of silicon powder. The method also accommodates the step of inserting a semiconducting material into the package preform and heating the semiconducting material component along with the package preform. The inserted semiconducting material component may be processed to define active electronic device areas on the component either before or after the step of heating the shaped package preform and inserted semiconducting material component. The package production methods of the invention provide the ability to produce reaction bonded structural and dielectric package components by way of a nitriding process that causes minimal overall shrinkage of the package. As a result, reaction formed electronic device packages of the invention may be shaped to finished dimensions before the nitriding process with complicated and tight-tolerance geometries of package structural, conducting, resistive, and capacitive components. The package production methods of the invention also provide the ability to interleave electronic device and packaging manufacturing sequence steps, resulting in increased manufacturing efficiency, as well as improved performance in the devices and packages produced. Device substrates or partially fabricated devices may be embedded into semi-finished packages, whereby completion of device fabrication coincides with completion of package fabrication. This makes possible the fabrication of active devices and circuits in a fully packaged environment.

The present invention provides an antenna including a relatively thin substantially planar electrically conductive first layer substantially lying in a first plane, and a relatively thin substantially planar electrically conductive second layer substantially lying in a second plane. The first and second layers are disposed such that the first and second planes are substantially parallel and such that they are separated by a distance d. The second layer is smaller than and overlies the first layer and defines a first region extending between the second layer and a portion of the first layer underlying the second layer. The antenna further includes a first dielectric medium having a relatively high dielectric constant and disposed in the first region, and a second dielectric medium having a relatively low dielectric constant and disposed in a second region extending between the first layer and portions of the second plane overlying the first layer and excluding the first region.

Mesa antenna

The present invention provides a miniaturized multilayer microstrip antenna that includes a stack of antenna sub-stacks, a ground element, and a plurality of electrically conductive segments. Each of the antenna sub-stacks includes a pair of substantially parallel outer principal faces. A sandwich of two relatively thin electrically non-conductive substrate elements, separated by a relatively thin electrically conductive layer, extends between each pair of parallel outer principal faces. The electrically conductive layer has at least one void region through which an electrically conductive feedthrough element extends. The feedthrough element also extends between the outer principal faces. The ground element electrically couples the conductive layers of each of the antenna sub-stacks. The electrically conductive segments are positioned between adjacent principal faces of two adjacent antenna sub-stacks in the stack, and electrically connect the feedthrough elements of the adjacent antenna sub-stacks, thereby establishing a first continuous elongated antenna element.

Multilayer miniaturized microstrip antenna

A two pole viad chip capacitor that is activatable from either of its sides having a plurality of ceramic layers in a stack, each and every layer having only two vias, a first via in a first region of each layer and a second via in a second region of each layer; a first conductor in each of the first vias; a second conductor in each of the second vias; a stack of first capacitor plates being on first alternate ceramic layers and each first plate being in electrical contact with a first conductor; and a stack of second capacitor plates, the second plates being on second alternate ceramic layers that are interdigitated with the first alternate ceramic layers and in electrical contact with a second conductor.

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Newton, MA, United States of America

William L Robbins