Cisco Technology, Inc.

Cisco Systems Inc.

Bti Computer Systems

William L Quackenbush

John T Chapman

David J Tsiang

Charles J Naegeli

Glenn E Lee

Hon Wah Chin

William P Cargile

Roland G Chan

Stephen C Porter

A lossless arbitration scheme combines IEEE 802.3 compliant Medium Access Controllers (MACs) with a centralized arbiter and out of band access control signaling to achieve a spatially confined LAN that looks to attached devices like an IEEE 802.3 LAN, but has no bandwidth loss due to collisions, no excessive collisions and greater short term access fairness than standard Carrier Sense Multiple Access with Collision Detection (CSMA/CD) LANs. Two such spatially confined LANs are combined with an IEEE 802.3 compatible full-duplex point to point link to provide communication between two spatially confined groups of devices without bridges and buffering even when the separation of the groups is not spatially confined.

Lossless arbitration scheme and network architecture for collision based network protocols

A pluggable port adapter is used for connecting PCI devices to a host system through a PCI local bus while also adding functionality to the host system. The port adapter communicates with the host system through a port adapter/host interface that includes the PCI local bus and an auxiliary bus. The auxiliary bus is used for controlling the additional circuitry on the port adapter. A PROM on the adapter card is used for identifying the port adapter type, serial number and hardware revision. The auxiliary bus is used for conducting JTAG testing and is used by the host system to program logic devices on the port adapter. The logic devices can be reprogrammed in the field by the host system to repair bugs and to enhance performance and/or functionality. A power control circuit on the port adapter is controlled by the auxiliary bus for conducting hot swap operations.

Hot plug port adapter with separate PCI local bus and auxiliary bus

Circuitry for affording access to a common passive bus by a plurality of computer devices connected to the bus. Each of the devices is provided with the circuitry, which operates in three sequential phases: a bus request phase, an address phase and a data transfer phase. Circuitry interconnecting the bus connections for permitting a device to initiate the bus request phase only if all devices superior to it are not in the bus request phase thereby establishing a priority ranking among the devices. The circuitry also includes a call back system wherein if a given device is unready to receive data when addressed by a source device, such device will, when it is ready, call back the source device that was previously and unsuccessfully attempting to transfer data to it. The call back system is also adapted to permit a device to wait for response from a single one of the other devices until such other device responds and then to call back other devices that tried to address it while it was waiting for a response from the single device.

System for controlling access to a common bus in a computer system

Growing community of inventors

Palo Alto, CA, United States of America

William L Quackenbush