Advanced Micro Devices Corporation

William L Price

Mammen Thomas

Christopher O Schmidt

Ronald Lloyd Schlupp

Peter S Gwozdz

An improved process is disclosed for making an integrated circuit structure wherein a trench is etched into one or more layers to electrically separate one of the devices in the integrated circuit structure from other portions thereof by first patterning silicon dioxide and silicon nitride layer on a layer of silicon. The improvement comprises isotropically etching the silicon layer to provide an enlarged shallow etch area undercutting the patterned silicon dioxide and silicon nitride layers. Subsequent deeper anisotropic etching to form the trench will result in a trench having an enlarged upper width which, in turn, prevents the formation of voids adjacent the upper portion of the trench during subsequent oxidation and polysilicon deposition steps. Possible creation of openings to such voids in the polysilicon during subsequent planarization is thereby eliminated thus avoiding undesirable oxidation of such voids and undesirable stress formation therefrom.

Process for formation of trench in integrated circuit structure using

A method is presented for fabricating a bipolar semiconductor device utilizing a combination of junction isolation, oxide isolation, stepper lithography and plasma etching to produce an integrated circuit device having reduced device sizes and increased performance. The method includes the steps of removing portions of a masking layer to expose surface areas of an epitaxial layer, where first type isolation regions are then formed; then forming second type isolation regions in the epitaxial layer, and forming base, emitter and collector contact regions, also in the epitaxial layer; and forming conductive lines on the base, emitter and collector contact regions.

Method of making integrated bipolar semiconductor device by first

Selected circuit elements and interconnections of an integrated circuit device are connected by platinum silicide fuse links which open when electrical power exceeds a threshold amount. The fuse is constructed by defining the fuse geometry in a polycrystalline silicon layer over a wafer substrate, depositing a layer of platinum thereover and then sintering the platinum into the polysilicon.

Process of making platinum silicide fuse links for integrated circuit

Selected circuit elements and interconnections of a integrated circuit device are connected by platinum silicide fuse links which open when electrical power exceeds a threshold amount. The fuse is constructed by defining the fuse geometry in a polycrystalline silicon layer over a wafer substrate, depositing a layer of platinum thereover and then sintering the platinum into the polysilicon.

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Saratoga, CA, United States of America

William L Price